Crosstalk issue in VLSI | Signal Integrity | crosstalk glitch | crosstalk Noise | part-1

[@baqirhusain5652]

May god reward you for this a thousand times over.....With no classes you are immensely helpful....Thank you sir

[@TeamVLSI]

Thanks a lot @Baqir for your nice appreciation. Please keep supporting!!!

[@carthyck]

The presentation you have provided is very informative. Thanks for the video.

[@TeamVLSI]

Hi Carthikeyan, Glad it was helpful! Keep watching, Keep learning, keep sharing...

[@jyothico8812]

Thank you for the clear step by step explanation.

[@TeamVLSI]

Thanks Jyothi.

[@EduQuantix]

Thank you sir, Greetings from Ecuador!

[@TeamVLSI]

Most welcome and happy to hear you.

[@durganaga9513]

Thank you sir. Nicely explained

[@TeamVLSI]

Welcome Durga!!!

[@habibakhatunnesaragi6259]

Well explained....

[@TeamVLSI]

Thank you @Habiba

[@mozart3575]

Great sir

[@TeamVLSI]

Thanks dear!

[@mozart3575]

Sir these details are not explained by iit professor's

[@mozart3575]

These much details*

[@habibakhatunnesaragi6259]

Great sir thank u....

[@TeamVLSI]

Welcome Habiba!

[@ArunKumar-wu4px]

Explanation is Superb ..kindly tell me (1)effect of cross talk on same metal layer and different metal layer...which is more significant

[@TeamVLSI]

Hi Arun, The spacing in same metal layer is lesser as compare to different metal layer. So cross talk from same layer will be more severe.

[@ArunKumar-wu4px]

@@TeamVLSI thank you

[@aakashek8526]

Thank you sir. Its awesome crosstalk seems to be very easy

[@TeamVLSI]

Most welcome 😊 @Aakash. keep supporting.

[@aakashek8526]

Sir can you create a vdo explaing difference of propogated clock generated clock And clock gating and its types

[@User--jm5916]

In which case undershoot happens that is victim net is constant 0 or constant 1 please clarify this one

[@TeamVLSI]

Hi Radha, The undershoot may occur when the victim net is at constant logic 1 and the aggressor switches from 1 to 0 logic.

[@User--jm5916]

@@TeamVLSI what about aggressor net switching, in this video u mentioned 0 to 1 at one time and 1 to 0 at another time please check this in the video

[@TeamVLSI]

Hi Radha, I have edited the previous response as it was not correct. Now try to link it with a time stamp @21:20 I have checked the video and I am guessing the reason for your confusion might be case-2 at timestamp @18:19 . But that is also correct I have here talked about the logic level of input of the inverter which is driving the aggressor and victim net. But if you see the logic level at points "A" and "V" then it will help to clear your doubt.

[@akhilalla3247]

how signal integrity effected by antenna affect? Antenna violation will come during fabrication because of that gate oxide will get damaged but how does it impacting my signal. I have watched your Antenna effect videos also. kindly brief me inshort with small example and Thank you for all your videos

[@TeamVLSI]

Yes Akhil, In case of there is antenna effect and gate is not completely breakdown.

[@TeamVLSI]

Please use time stamp of video to indicate a particular timing of video.

[@durganaga9513]

Hello sir, is substrate failure also possible with this crosstalk?

[@TeamVLSI]

What is Substrate failure?

[@pavankumarVilasagar]

we see glitch violations between same layers, why not between different layers?

[@habibakhatunnesaragi6259]

I suppose due to static logic ....in same metal layer

[@TeamVLSI]

Hi @Pavan Thank you very much, for asking such a good question. Actually crosstalk may occur to a victim net from the same metal layer nets as well as inter metal layer nets. But the effect from inter metal layer nets is lesser as compare to same metal layer net because of the distancing between them and routing direction of metal nets. For Example, suppose victim net is in M4. so crosstalk glitch may occur from following nets. 1. Adjacent M4 nets. 2. M3 and M5 (But these are not routed in the same direction as M4 , so area of mutual capacitor will be very less and distance is also large compare to point-1, so mutual capacitance is very less as compare to point-1) 3. M2 and M6 ( These are routed in same direction as M4, But now distance is too large) So most dominating contribution is from same metal layer. Hope I made it clear. Let me know your view on it.

[@pavankumarVilasagar]

@@TeamVLSI Thank you for the explanation