Length Tuning | PCB Design Basics Tutorial

[@chromatec4311]

Thanks again Zach. I think the AD design rules work very well indeed for all matched length requirements. I use a lot of 12Gbit/s SERDES so choice of trace width, spacing and length become important additional factors that are influenced by PCB stack-up and FR4 losses. A high-speed tutorial covering these topics would be good!

[@Zachariah-Peterson]

That's a great idea, I have a big list of layout example videos that we have to do but I will get this on my list!

[@asmi06]

I recommend matching by delay as opposed to length, especially for parallel buses like DDR3/4, because chances are you are going to have to route traces of a group on different layers, and so they will have different propagation delays because signals on outer layers are about 10-15% faster than on inner layers. Also it seems that Altium does not account for via z-length delays - not sure if it can be turned on or not, which can also lead to additional skew - take that 4 layer board shown, those signals that go via bottom layer will have their path 1.6 mm (standard PCB thickness) x 2 (as signal "cross" the PCB twice) = 3.2 mm longer than those on a top layer, and that alone adds about 20 ps of skew. This is not a big deal for slower interfaces, but once you get into 1GHz+ range (say for DDR4 interfaces, which often go beyond 1GHz), this skew becomes significant enough to worry about. This is less of an issue for differential pairs as they are pretty much always routed edge-coupled on the same layer, but they have a different problem - namely dynamic phase skew, when signal edges don't physically propagate next to each other due to difference in traces geometry. This is why it's always recommended to add length matching as close to the place where length mis-match occured as possible, such that edges would travel together for as much of a differential trace length as possible. Again, for slower interfaces and/or shorter traces this is not very critical, but once you get to a backplane territory, these things become critical.

[@Zachariah-Peterson]

Bro, you're posting all the stuff that's going into the follow-up video!

[@asmi06]

@@Zachariah-Peterson That's great! Not many people read comments, so it will be great if you make a video explaining these things more thoroughly than a comment can. Keep up the good work you do!

[@TheDigital19]

i'm very interested in the Z axis delay too - i think you can add it manually to vias but AD doesn't do it automatically (yet). comparing it to other tools on the market, AD does a really good job at this stuff, very accessible and easy to use

[@AltiumAcademy]

​@@TheDigital19 Yes you can add it manually, just select a via and look in the Properties panel. We just did a video talking about this point with the z-axis Dk value in the backdrilling video and there is another one where I look at via delay specifically, it should be ready soon.

[@vatsan2483]

Loved the rick hartley reference!! Just in my opinion and my preference, the timing tuning is what really is the thing that matters in differential pair.. And technically we do length matching just to map to similar arrival time as pair travels in same dielectric material.. I am glad Altium actually introduced time matching tool for diff pair in new versions..

[@saeidesekhavati1518]

Thank you very much from making this video!

[@AlbertRei3424]

Maybe a video on the notion of 'Timing Budget' ? Thank you.

[@davidlee1361]

Thanks Zach for the excellent tutorial! I am curious as to why tool primarily use accordion, trombone, and sawtooth patterns to address length matching. Are there any particular reasons for not considering spiral patterns or other alternative patterns in this context?

[@Zachariah-Peterson]

They are used because every other CAD vendor uses them, and I think people are just more familiar with these. I have never heard of a spiral pattern, but I think it might be similar to a trombone structure?

[@muralikrishna2549]

How to calculate the Trace width for the pulse high current ? Like 100A pulse current for 20% duty cycle.