LMARV-1 reboot part 10: Some errors, some schematics

A somewhat short video this time, catching some errors, and trying out some schematics.
nMigen exercises: github.com/RobertBaruch/nmige...
github repo for code: github.com/RobertBaruch/riscv...
RISC-V specs: riscv.org/technical/specifica...
nMigen tutorial: github.com/RobertBaruch/nmige...

[@dnwheeler]

Coincidently, I'm wearing a Weyland-Yutani shirt right now, too. "Building Better Worlds"

[@obiwanjacobi]

If the 'totally generic' board idea doesn't work, you can at least combine similar types of boards. Like have one register card that can be used for all registers - etc. Nice progress, thanks for taking us along.

[@LaserFur]

it's interesting in how you are now looking at one of the things that was done in the early computers. to reduce the number of different types of cards they had the cards designed so that they could do different things depending on how the backplane was wired.

[@smunaut]

Your ring oscillator example has an even number of stage :D

[@marknn3]

Then it's a flip-flop :-)

[@TomStorey96]

"How's that, cat?" 😸

[@truezulu]

As always: Very interesting!

[@marijnstollenga1601]

Can't wait to see the first cards!

[@Jonas_Meyer]

I would put some not mounted footprint on the PCB for some larger MLCC capacitors just in case you need them.

[@miharu3188]

Flava tech live :)

[@abeditani8293]

6:40 yes that what I was see it wrong from the start . You need outside synchronize controls

[@KingJellyfishII]

Easiest way to solve this is to have the entire CPU as a ROM, with the program as the address and the output as the data :p

[@LaserFur]

a 4GB static rom?

[@KingJellyfishII]

@@LaserFur 4000000GB more like

[@merseyviking]

@@KingJellyfishII You can buy them on eBay, totally legitimately. :)

[@KaneYork]

Register file X/Y/Debug should fit on one card each, right? But yeah that makes sense for every internal register

[@sabriath]

I would be impressed if this were built as a mechanical or fluidics computer.

[@naikrovek]

which Surface device are you using for recording? Or I guess it could be a Wacom device. GIMME DEM HARDWARE SPECS BRO

[@RobertBaruch]

Wacom Cintiq 27QHDT

[@hjups]

Shamt is encoded in the same field as immediate. So you can just feed the rs2 / immed bus to the shifter. For the gold plating, you want something called "gold fingers" not ENIG plating. The ENIG will wear down just as quickly as solder plating. Instead, the gold fingers place a thin sheet of gold film over the pads (I believe its sort of like a laminate) which will last much longer. Good find on the card edge connector, those look like they will work very well. Having four of them may make them much harder to insert though... could you perhaps consolidate busses by sequencing the sequence logic? You don't need all of those values at once all the time, right? Also, for a lot of the logic, it may be worthwhile to just build a generic PLA element. If you want to save cost to make it re-usable, you could place 0 ohm resistors at every intersection to select how the PLA is configured. You could potentially even implement the big gates not as 74 series, but as transistors (since large input gates are trivial with transistors but need to be done in a binary tree with 2-input gates). I suspect that would be a lot faster than a ROM, and if you can simplify the logic equations, it could potentially allow you to sequence the sequencer into multiple steps to save buses / wires.

[@marknn3]

I think the generic cards can be done with only 3 connectors each. The Sequencer will have dedicated slots for each card type, and route the required signals to the individual cards. Maybe there is an overlap in signals that I don't fully see, but it is worth to try this puzzle.

[@hjups]

@@marknn3 There are definitely ways to reduce the number of signals... he really only needs branchPC, PC+4, and EPC. EPC can come from the CSR where the CSR either outputs mtvec with cause, or mepc. The branchpc takes care of branches, jumps, and auipc, etc. That could probably be generalized to having two registers on a single card. Each with 3 input options as well as keep (so that's the 4th). Reset to 0 can be done if he uses the OE signal, and ties the register output to 0. So you set OE = false and input = keep. For mtvec, 1) he doesn't have to support vectored interrupts (it's not required by the spec), and 2) he doesn't have to support arbitrary vectored instructions. What I mean by that, is he could place cause and mtvec in the same register, and just have the ability to output or not output different parts of it. Make it a 32-bit register, where IRQ is the msb, but the backplane shifts the output by 2. He could also put the multiplexer for a single output on that register card too. There are ways to reduce the wires required.

[@davefiddes]

Have you given any thought to debugging the system once it's been built? Your original idea had excellent blinkenlights which seems pretty much impossible given the number of signals you have now. Having some way of hooking up a logic analyser to verify correct operation seems like a good idea to me. Yes I realise that your modelling and formal verification should minimize any errors but there's going to be a heck of a lot of hardware to trace through if it's not perfect.

[@tomaszcichocki8281]

I'm wondering, have you considered using github.com/xesscorp/skidl or something similar? I admire your KiCAD proficiency and schematics have some visual appeal for me, but wouldn't it be easier to create netlists straight form python? Possibly from the same codebase that describes circuit in nMigen... I can imagine having "elaborate" method and "generate_netlist" next to each other...

[@wChris_]

i hope you wont prematurely by any PCBs until everything is Designed and pretty much finalized

[@RobertBaruch]

Yeah, I've been burned way too many times.