Logic Synthesis flow | RTL Synthesis flow | RTL2GDS | Design Compiler (DC) tutorial

[@thatdrownedbiscuit]

Sir The content is top-notch But maybe can we eliminate the background noise?

[@AbhishekKumar-hh8xc]

Thanks a lot for this. I am from simulation background. But I was able grasp most of the things you explained in synthesis with your explanation

[@manjunathac3281]

Very good explaination sir. Thank you for uploading this

[@TeamVLSI]

Thanks Manjunatha!

[@byambajavr6519]

Excellent tutorial sir. Thank you :)

[@TeamVLSI]

Thank you.

[@pratibhajha617]

Hello sir can you please explain the reasons why we are writing constraints to tools and explain thru one small project

[@shri1527]

whats the difference between link library and target library?

[@prasadgadipalli7077]

Target library is subset of link library. Target library contains stdcells for mapping . Link library is to resolve references or subdesigns or re usable building blocks or macro libraries or memories

[@yprashant66py]

Great explanation!

[@TeamVLSI]

Thank you :)

[@bishweshwarprataptasa9918]

Thank you for nice explanation.Can you tell me What is Check design in Design Compiler?

[@TeamVLSI]

Thanks Bishweshwar, You can check the explanation in our blog. www.teamvlsi.com/2020/08/sanity-checks-before-floorplan-in.html

[@bishweshwarprataptasa9918]

@@TeamVLSI Thanks...

[@Narennmallya]

Thank you sir. One doubt In this case input is design constraints provided by Vendor(say Synopsys) and output obtained is SDC file which is again a design constraint so how are they different sir, are they different only in terms of attributes or what? and design constraints are read only files like you said, since we are not allowed to change it. and how about sdc?

[@jainyjose4841]

Sir can you make a tutorial on SOC design

[@TeamVLSI]

Hi Jainy, Yes, In RTL to GDS flow video it is already covered, please check the video.

[@raghav9182]

Great video again. Sir, can share something, material/video etc. on the 'timing arc' in standard cell library and how to modify them?

[@TeamVLSI]

Sure, will try. Thanks for the request!

[@jagruthgowda3006]

Hello Rajesh Sir 1.In which stage of synthesis clockgating cells gets added. 2.On which basis tool will add clockgating cells. 3. Does RTL engineer write verilog code to place clock gating cell in perticular region of your design.

[@prasadgadipalli7077]

1. Clock gates are added after elaboration and before opt and mapping. 3. There are two types of clock gates Architectural clock gates which are added by rtl and inferred clock gates which are added in Synthesis

[@mahimasoni6145]

content is good but there is too much background noise, because of which not able to understand properly

[@TeamVLSI]

Thanks Mahima. Will take care on your feedback.

[@avinashmaheriya8737]

Explanation about the concept is really good. But Sound Quality of video is very Poor.

[@TeamVLSI]

Thank you Avinash Noted your feedback. You will find good audio in upcoming videos.

[@avinashmaheriya8737]

@@TeamVLSI Thank you very much.

[@vijayak5359]

Your videos are really good and good details explanation but Poor audio quality plz.....find it this problem sir o:-)o:-)

[@karthickramki4062]

difference between compile and compile_ultra

[@TeamVLSI]

Compile_ultra is more advance than compile, and it provides better QoR. For more specific details, please refer the DC user guide.

[@Kalyan14145]

Lots of noise is disturbing But nice content