Logic Synthesis of RTL | Synopsys Design Compiler | Synopsys DC | dc_shell | DC Tutorial

[@aratidesai9146]

Thanks for all your videos. All videos are very useful

[@TeamVLSI]

Hi Arati, Glad you like them!

[@minhthien7073]

Thanks you. It is very helpful to the new like me.

[@venoum0]

Thank you.Very informative videos

[@TeamVLSI]

You are welcome Debolina. Keep supporting, Keep learning.

[@allachandrahas7951]

Thanks a lot for your efforts

[@TeamVLSI]

Thanks a lot @alla !!

[@Ganesh_Linga]

Tq so much of u sir... 👍

[@prashanthreddy2163]

Your videos are really helpful. Could you also please make videos on learning TCL script

[@TeamVLSI]

Yes Prashanth, But it will take some time.

[@lavanyaekkandolla8512]

Hi, how to read the multiple files ( hierarchical design) in the dc shell? Is there any option to read the filelist?

[@pullepujaswanth5035]

sir, what about the zero wire load model that we use and can you differentiate different wire load models?

[@mohannadasar6126]

You didn't associate the create_clock SDC command with the clk port [get_ports clk], is this why the timing report showing unconstraint path?

[@junqichen1790]

thank you sir，it is very useful. I want to know if there are relevant documents

[@gopalag6916]

How to clear in unconnected error

[@kailashprasad1137]

Can you tell me how to pass agument to the tcl file in dc_shell. I m running dc_shell like this. dc_shell-t -f /home/vlsi2018/BootLoader/syn.tcl

[@TeamVLSI]

You may open the dc shell first , then in tcl command window you can source the tcl file with argument.

[@naveenkabra5037]

please cover all these using VHDL codes Thanks you

[@dharamvirkumar558]

Hello sir, i am facing a problem when i am synthesizing a full adder in cadence genus..since it is a pure combinational circuit..do we still need to provide clock definitions in the .tcl file. Or how to synthesize a combinational circuit without .sdc file?

[@TeamVLSI]

Hi Dharamvir, You can define a virtual clock.

[@thejanaidu4381]

Please cover all features of design complier sir.

[@TeamVLSI]

Hi Theja, Thanks for the feedback. Currently I am not getting chance to work on Design Compiler, But Yes , When I will get chance to work on it, I will work on your suggestion.

[@thejanaidu4381]

@@TeamVLSI any way ur explanations are really good. If you can. Please explain icc2 tool