Logic Unit PCB - Making an 8 Bit pipelined CPU - Part 90

[@IslandHermit]

Watching surface tension pull those SMCs into position never gets old.

[@weirdboyjim]

I know right!

[@ray30k]

Watching you make the PCB designs is absurdly satisfying, thank you very much for sharing this!

[@weirdboyjim]

Glad you like them!

[@Minoz99]

It must have felt great to take away all those breadboards in a single go, you got the design right at the first try too!

[@weirdboyjim]

Indeed it was thanks! But not quite as satisfying as this: kzbin.info/www/bejne/jKWydIyYacmXbtk that bundle of wires was getting difficult to manage.

[@KingJellyfishII]

I find it oddly satisfying shrinking everything down into PCBs. Great work, especially with almost everything so far working first try!

[@weirdboyjim]

Don't jinx it! The next board is going have a lot of components on. One thing I find interesting is the difference in scale down proportion for different types of components. Thanks for the support 1k!

[@rlbjr898]

Yay! Great stuff James! Not to jinx you, but I'm really glad that the last two boards have worked first time... that has to be a really satisfying feeling!

[@weirdboyjim]

Thanks Bob! Really keen to get the last of the ALU done, pretty close to having the core of the cpu all on pcb although there is one bit i'll be revisiting.

[@alessiocaffi5992]

well done James, your CPU is too nice, it deserves a 128x64 dot LCD. (BTW ,saw your RISC-V comment, yes nice stuff ) Cheers.

[@weirdboyjim]

It's going to get better than a 128x64! ;-)

[@alessiocaffi5992]

@@weirdboyjim Glad to hear , maybe I skipped some of your earlier video .

[@lawrencemanning]

Awesome stuff! The diode matrix is going to be a very interesting section of the overall design.

[@weirdboyjim]

Thanks Lawrence! The control board (which includes the the diode matrix) is of for manufacture at the moment, quite keen to get that one in.

[@brandonmack111]

I was literally thinking how I was glad I didn't have to wait to see the finished board, when you said the very same thing 😆 It's great to see how much more space-efficient PCBs are than breadboards (though the reason is pretty obvious)

[@weirdboyjim]

One of the reasons I went with SMD was to keep the physical size under control.

[@AjinkyaMahajan]

Great work. And completed with perfection. Cheers ✨✌

[@weirdboyjim]

Appreciate the support as always Ajinkya.

[@jerril42]

Thanks James. It's starting to look like a thing. Hopefully the next two boards turn out as well. Take care.

[@weirdboyjim]

Fingers crossed! It feels like every spare minute has been EDA work recently, that and adding some features to the assembler.

[@miege90]

It is probably fixed by now, but just in case: the bit-7 output LED is the wrong way round 16:03

[@weirdboyjim]

Yep, can't remember when I fixed that though. Pretty minor thing.

[@DustinWatts]

@03:58 An answer to your question might by; because the footprint has a standard prefix of U. Probably used a custom footprint? You can edit that footprint to have the default prefix of C. If you look up the footprint you are using in the library and click "Edit", on the left you can see under custom attributes something like "U?". If you change and change that to "C?" and save it, the next time you use the new saved footprint you will have it starting with C. Again, great progress! :)

[@weirdboyjim]

All the caps I've grabbed out of the lcsc library seem to have "U" thought there might be a reason. May even be a language thing.

[@DustinWatts]

@@weirdboyjim U is the default prefix when a new footprint is created so maybe someone forgot to change it?

[@FrankGevaerts]

Getting really close now! I'm still surprised every time how much smaller those boards are than the breadboard build. I should be used to it by now...

[@weirdboyjim]

I know! Might have been slightly easier if I moved the divide between the shift and logic units a couple of millimeters to the right.

[@FrankGevaerts]

@@weirdboyjim Next time :)

[@tinygriffy]

13:14 no, you don't ... would be interesting though to see you in lab coat and rubber gloves handling beakers with caustic substances etching motherboards .. or in the shop drilling and riveting 152 vias :D .. these board manufacturers made prototyping so easy for us, it's a bliss. But it would be quite a sight i bet ... all your boards hand made in shiny copper with transparent solder mask...

[@weirdboyjim]

Maybe a future mini series to experiment with some home pcb production techniques, but not before I'm finished with this cpu build.

[@rickdearman9992]

Another great video! Unfortunately for me, it highlighted a mistake I'd made in my own ALU design and I need to yank some wires out and start the logic part again. Oh well, 3rd time lucky.

[@weirdboyjim]

Sorry to hear that Rick! Are you using the same 4:1 selector trick?

[@rickdearman9992]

@@weirdboyjim yes I am. But I wired up the inputs wrong. Still i think it will work out better because it has made me think about things a bit more and I see some improvements.

[@erniepasveer8027]

Impressive !

[@weirdboyjim]

Thanks Ernie.

[@retrocomputeruser]

Not sure if this will help when connecting grounds together. I always leave the grounds unconnected then do an upper and lower ground fill after everything else which auto connects them where possible (It does in Kicad and EDA should). Any remaining unconnected grounds can usually be achieved with via's to both planes or a simple re-route of a Net.

[@weirdboyjim]

I used to do that but hit a problem on one board where the ground routes were really complicated. Now I'm using 4 Layer boards this is much easier!

[@scottjcrouch]

As a complete novice, one of the things I've been surprised by while watching you develop your designs is the use of small delays with a few NOT gates to satisfy timing constraints. In the back of my mind it felt a bit "hacky" because my intuition was built upon operations always being aligned to a clock edge (so a theoretically perfect digital circuit could be clocked to arbitrary speeds, but introducing the concept of delays suddenly puts an upper bound on that). Is this technique something that you could expect to see in high-speed silicon?

[@weirdboyjim]

That is a great question, and one where I have to remind you that I am not the fount of all knowledge in this regard. I've been learning as I go and this is one of the areas I've been least comfortable with. I started of thinking about the clock signals in the way you describe but past a point it became clear that you have to look beyond that. Time is (for all intents and purposes in our circuits) analogue, some circuits will respond faster than others and the places where I've done this are dealing with those situations. I've started thinking about the clock less as the hard definition of time and more as a gating system that lets you keep everything synchronised, you are using it to make the fast components wait for the slower parts of the circuits. I can't really tell you how "legitimate" the specifics of what I've done are, but I have seen people with vastly more experience do similar things (that made me feel better). On really high speed boards the experts take it to the next level and start adding little wiggles onto the traces to ensure that signals arrive at the expected time. Definitely avoid it where possible, make it as minimal as possible. I need to revisit one location where I suspect I put more delay than was needed in.

[@m1geo]

This is not how it is done in a modern digital design. In an FPGA or ASIC, this kind of thing is very scary! Typically you specify setup and hold times, clock frequencies and domains, and propagation delay details. The toolchain then works hard to ensure that the result of any logic will be valid and stable (as per the setup time) and will remain valid (as per the hold time). The tools will show you the time between when the data is valid and read, and is called 'slack'. This slack can be negative, meaning the signal path is slower than the required time, or the data isn't valid until *after* it is read. Such a design is commonly referred to as 'failing timing'. The FPGA toolchain will try to help, by physically using resources closer to each other, so the path is shorter and thus quicker. Other techniques include adding registers into the design, so that the data is retimed to the clock part-way through the logic. Typically negative slack is caused by lots of combinatorial logic between registers that takes longer to propagate than the clock period (plus setup/hold) or the FPGA is becoming congested and the place and route is using logic elements further away than is ideal as closer ones are used. Here, floor planning and manual partitioning (guiding the place and route state manually) can help. Fundamentally, the designer would have to (a) come up with an equally functional design that works faster, or, (b) ease the timing constraints if they're overly tight. For more details, Google "FPGA negative slack".

[@AiOinc1]

Please tell me you're going to convert the diode matrix into a something more elegant than the mess of jumpers on that premade board

[@weirdboyjim]

What's wrong with my beautiful diode matrix board? ;-) Did you see the soldering mess it replaced? Hopefully you won't be disappointed with what I've done for that, PCB should be next one you see.

[@AiOinc1]

@@weirdboyjim It's definitely a fictional solution but I would rather see it without the jumpers

[@TomStorey96]

Traces coming out of the side of the pads really triggers me 😄

[@weirdboyjim]

I know how you like to complain about things tom, I'll be sure to do it more in future 😆

[@TomStorey96]

🤣 please do. Actually I have a question. What size is your flux syringe? The success you are having with reflow soldering has inspired me to buy some more tools lately and give it a go myself. Got a hot air station, just need a couple more bits and pieces to help make the job easier and flux is one of the last items on the list!

[@m1geo]

Agreed. I shudder at that, too. And tracks that meet pads not at 90-degrees. Not only do they cause acid traps (probably not a problem these days) but they look ugly! 🙂 But I realise that's is a personal preference and doesn't make any difference. 😂

[@axelBr1]

That's triggering you? How about the layout of the input and output LEDs and logic being different on the two ALU logic boards? I'm coping by at least the input LEDs on the LHS board are on the left and on the right for the RHS board. 😂

[@twobob]

heart emoji. time for some more paste.

[@weirdboyjim]

:-)

[@TheDefpom]

Have you considered doing pcb sponsorships to save yourself some money, nothing like free PCBs delivered very quickly 👍🤓

[@weirdboyjim]

I've had a couple of approaches from pcb companies but I want to be careful about picking the right partner under the right circumstances.

[@TheDefpom]

@@weirdboyjim just stipulate how you want to do it, they will either accept it or not, if you do anything try to keep it in tune with the channel, and not like some kind of advert break, as you have probably seen mine are mostly just mentioning where I got the PCBs with a link in the description, with one or possibly two subtle pop up banners, I didn’t want have anything disruptive to the content,