Master-slave JK flip-flop

[@sodapopinski9922]

Its amazing how quick the size of the circuit grows, for every problem, all that for 1 bit of info

[@MichaelOReilly01]

As an electronic engineer I appreciate how you simplify your explanations and have brilliant videos which helps me when ever I try to explain something to college students 👍

[@someniceguyon]

My progress is slow… But I am learning so much from your videos. I love that I can jump into your deep end videos, and then watch these for clarity when I get lost.

[@abdelrahmangamalmahdy]

i always enjoy watching your videos late at night xD

[@yoianrhodes]

While high? ... or... nvm

[@abdelrahmangamalmahdy]

yo ianrhodes I don't get you!

[@lukasrussell5905]

three of us

[@jdaniele]

Me too! Thanks Ben, you are really clear and effective!

[@Cookieglue]

Same

[@kingfalconkhan]

I like how you do something and then come across a problem and then try to solve it, it gives us a great insight into various reasoning and problem-solving.

[@realdragon]

Latch -> flip-flop -> JK flip-flop -> master-slave JK flip-flop

[@Natture01]

where does the D latch fit into that?

[@abhinayragam8078]

​@@Natture01 latch -> SR latch ( basically to set or reset the latch ) / D - latch ( if enabled whatever D input is output is layched ) - > flip flop - > SR flipflop ( works just fine , except for when both set and reset are high , making it unpredictable) / J-K flip flop ( theoretically eliminates the unpredictability by accounting for feedback from output , but the clock is high for long enough time/ wide range making it practically unpredictable -> Master slave JK flip flop ( completely robust and predictable behaviour )

[@zachsargent3520]

My logic professor is complete garbage. Thank you so much for these videos. I finally understand this concept and so many others through your videos!

[@enginstud8852]

at least you had one

[@deltakid0]

@@enginstud8852 at least you don't pay to have a garbage professor

[@enginstud8852]

@@deltakid0 You can pay to make engineering studies and eventually doing management studies instead, this is what happens in France

[@deltakid0]

@@enginstud8852 no, you're wrong, I can't pay

[@enginstud8852]

@@deltakid0 Where do you study?

[@techieexplainer]

Please continue this series and add new features to this computers

[@Neverforget71324]

When I was in college, my professor went over this quite quickly... without any practical examples (i.e. showing the waveforms on an oscilloscope) and I never completely got the concept. Thanks for making me finally understand all of it!

[@shubhamduttasd]

This is going on as a very good series. It easily covers a semester course on digital electronics.

[@jeffbarnett6158]

SOOO excited! I'm guessing from these latest videos that he subtly building up to the Program Counter.

[@ArsyadKamili]

I always love it when KZbinrs uses an oscilloscope, complex or not. XD

[@Sorazal23]

The only clear and properly structured explanation I could find for Flip-Flops. Really awesome content thanks!!

[@slayerpuppet1694]

You are just fantastic, the way you imparted the knowledge was genuinely intriguing. Thank you so much.

[@crocellian2972]

Again, holding the clk showed beautifully how things work. Better than my $3K scope. I'm building that clk Board tomorrow.

[@memesalldayjack3267]

i was trying to figure this kindof stuff for myself ever since i saw that 'rising edge detector' on the flip-flop video iirc, and i'm glad to see i was getting close, i thought about 'falling edge detector'

[@May-sy9jk]

thanks Ben,you are awesome!love you.

[@JasonMasters]

Subscribed. :) I'm quite enjoying this series. What I'm waiting for is when you get to the instruction decoder, but I'll possess my soul in patience since I've enjoyed watching all of your videos so far. I've already figured out something I didn't understand before, which is how to make an ALU. I should have figured it out for myself earlier, but now I realise that you can just hook up some logic to perform all the ALU functions you could possibly want immediately, and just select which output you want based on the instruction register.

[@PinoMelrosso]

thank you very much for all those enlightening videos! i've learned a lot about the "innards" of computers through your videos. given that i've been working with computers for a long time now, that is quite an achievement from your side.

[@pavelhegler]

You have mastered lvl 100 of explanation :)

[@louco2]

Great stuff, thank you for taking the time!

[@SaucemanSauceman]

Thanks Ben ,your vids have helped me alot!

[@MasterHigure]

If you want your computer to fully "tick" on the rising edge of the clock, would it make sense to build an RC edge detector on the CLK input to a MS-JK-flip-flop? Is there any downside to having components of the computer actively doing something on the downtick of the clock?

[@maximilientirard1720]

Yay, no more racing! ... But! What if the NOT gate used on the clock signal has a looser sense / lower tolerance for HIGH than the and gates? All logic gates have some manufacturing differences, right? If that is the case, and if the clock signal spends a sufficient amount of time in this state (where the AND gates from the 1st stage SR latch considers the clock to be high, and the lone NOT gate considers the clock to be low), would that mean that there would be some more JK racing? I'm guessing this wouldn't be an issue in most cases, but still. Who knows? (Not me, for sure!) Loving these videos!

[@frisosmit8920]

That also seems a problem to me. You could solve it however. If for example you add the output of the inverter with a comparitor which checks if the clock voltage is less than a certain low value. Then the second SR latch would only be enabled if the clock is less than a certain voltage

[@frisosmit8920]

I guess you won't need that inverter then either

[@zoltankurti]

Or just use the simple RC edge detector before the and gates.

[@smithw7003]

If this doesn’t work for you keep reading. I built this even though it won’t be a final component of the computer, because I want to understand the logic. I also built the J-K Flip Flop because I wanted to perform the debugging with my scope. Of course, Ben does not walk through the build process on this Master Slave Flip Flop step by step and I would not expect him to at this point. I like trying to follow the schematic along with viewing the finished board. Unfortunately on this build, once I was finished, it did not function properly. Rather than examine the schematic, I simply compared my build to the video. I could not find anything wrong. Finally, I took a screen shot of the board and then blew it up larger. This is how I discovered that I completely missed the jumper on the 74LS02 between pins 3 and 4. It was so small it just blended in on my video. Hope this helps someone else that might miss it. Moving on now to the next video. Very much enjoying the build and the knowledge gained.

[@MarkusBurrer]

This series is awesome

[@saidamir4181]

Ben can you put a list of all the ICs used in these series. lovely stuff, keep them coming.

[@StaDo0815]

There is one in the description

[@anthonymartin6237]

He's back!

[@paulbaker916]

Brilliant videos. I have a new favourite channel.

[@Berred]

VERY good explanation and a lot of practice !

[@COMB0RICO]

Thanks from Texas.

[@FalcoGer]

There is a problem with this. As the clock transitions between high and low you might have the inverter interpreting the clock as one thing and the first and gates as the other, making both flip flops enabled or disabled. You'd want 2 pulse generators (one for rising and one for falling edge).

[@victorsantanpagay5811]

its very understandable tutorial sir keep the good job

[@shreyaskudari1470]

This is a negative-edge triggered flip-flop. Is it possible to make it positive-edge triggered by using the NOT gate for the clock pulse of Master instead of the slave?

[@miniaturenature2507]

How we make this circuit on bread board . I mean to make this circuit which ics are used

[@nedisawegoyogya]

i thinkk so

[@katemoon7476]

@@miniaturenature2507 You buy the 7400 series chips from Jameco and you assemble it.

[@florianheiter2062]

2:27: Aren't master and slave gonna be active when the clock is already high but the inverter is still switching from high to low?

[@kieraleahy6795]

As I understand it, this isn't an issue because it takes longer for the signal to propagate through the first SR flip-flop than it does for the inverter to switch. Afaik the inverter will switch faster than even just one of those AND gates, since the transistor logic is less complex.

[@florianheiter2062]

@@kieraleahy6795 Yes, you're right. Thanks

[@Huntracony]

I guess you could still add an edge detector, and have the second one switch when the edge detector turns off.

[@mohamedgendia4274]

You are my master ! I love you

[@lucasbarbosa4509]

This guy had for sure got his inspiration from Code by Charles Pretzold

[@SD40Fan_Jason]

It would be swell if KZbin could maintain your "up next" videos in order. For me, the next video is the 555 astable multivibrator - part 1, which ironically is not only a video I've already seen, but it's also the video that brought me to your channel. Not sure why youtube hates me...

[@hpsmash77]

poor you

[@ophello]

Can’t you use a Schmitt trigger to clean up the clock signal?

[@Neverforget71324]

Master to slave: "Here's your assignment... no rush... you have an entire half clock cycle." I think it needs to be renamed to "Enlightened Boss - Happy Employee JK Flip-Flop".

[@davadoff]

Has no one noticed the circuit at 5:21 must be wrong? J can’t set Q high: the bottom AND gate will always output low because of the low input from Q. With Q & J low, the bottom NOR gate outputs high making K & the top AND gate irrelevant.

[@gloubiboulgazeblob]

Interesting ! Trying in a simulation software (simulIDE), it only works if, at the beginning, J is high and K is low (or K is high and J is low)

[@burninhell4448]

Couldn't you just use a capacitor on the clock of a normal JK flip flop as you did with the D flip flop? Or would it be difficult to tune?

[@maximilientirard1720]

Do you mean using a capacitor-resistor combo as a rising edge detector for the clock? If so, yes, it would be difficult to tune, at least on a bread board. That would be why a master-slave JK is necessary. Ben explains this in the previous video in this series called 'JK flip-flop racing'.

[@jacclawrence2951]

this is amazing thank you

[@Myzreal92]

Is this a part of the 8-bit computer or is it independent? I believe it is, but just wanted to make sure as it's not added to the playlist

[@scitwi9164]

In the 8-bit computer he uses digital counters (e.g. the program counter and possibly the sequencing unit), which are built from T flip-flops, which are pretty much JK flip-flops with both their inputs connected to the binary 1 (logic high) signal all the time, so they toggle with each clock pulse. That's why he needed to explain the JK flip-flops first. But they're not necessarily a prerequisite for the 8-bit computer, so those videos are not on the 8-bit computer playlist. (Same as with RS flip-flops.)

[@conorkerin5277]

Could you use a capacitor and resistor on the feedback to slow it down instead of the master slave circuit?

[@etbilu6265]

in digital circuit , time is a luxury !

[@JackEnneking]

I'd love to hear your explanation of 74LS vs HC and others. Why do you use LS for these projects when most people seem to recommend HC? What should I get if I just want to mess around with logic?

[@chitlitlah]

The LS series still uses bipolar transistors for true TTL but uses less power than the original 7400 chips. The HC series is high speed CMOS which emulates TTL. The CMOS versions use even less power and are considerably faster than their TTL counterparts, so they're more often used for their performance in products you buy at the store. However, they're a lot more sensitive to static discharge which is pretty important when you're building something on a breadboard and handling the chips and connecting wires a lot. Additionally, CMOS tends to prefer 3.3V instead of 5V for power, though the HC series can handle either. If you're just messing around trying stuff on a breadboard, the LS series is much better in my opinion for its greater durability.

[@michelfug]

Why do you use resistors with the LEDs in this circuit? I thought you've explained in a previous video that it's not necessary when it concerns the output of this kind of ICs.

[@petrickoliveira1351]

Well, probably 4 years later either you already know the answer or don't care about it anymore, but anyway, this is more for myself: I don't know what video you're talking about, but it's probably cuz some ICs have resistors on the output, and some doesn't.

[@michelfug]

@@petrickoliveira1351 Haha, nope, still an open question! So thx for the response! The other video I'm referring to is about the SR latch (5y old atm), and his remark on LEDs and resistors and ICs is around the 1:15 mark in that video. I guess the answer to this question is hidden in the datasheet of the chip used here (the 74LS02), but I have only limited experience reading those kinds of documents.

[@andreamazzai1969]

@@michelfug I have learned that most TTL chips don't need resistors in order to drive a LED, *but* if the output is also connected to the input of another chip, you might encounter issues because the LED will "drive down" the output voltage at a level that some inputs might not recognize as a high logical state.

[@davadoff]

This is an easy one: the LED resistor sets the LED current (and affects power consumption of the whole circuit). LEDs will easily destroy themselves if you don’t limit their current.

[@davadoff]

@@petrickoliveira1351 if an IC cannot supply or sink much current, you might get away with no resistor. At best, it’s OK for prototyping but LED power consumption might be x10 higher, for example.

[@correajr6955]

Great Ben!... Let me try to guess... the next part of the SAP-1 is gonna be the program counter?

[@MattyFez]

Would you be able to demonstrate the breadboard master-slave JK flip flop on the oscilliscope?

[@byallmeansengineering8475]

Hello Ben, you stated that there are 2x 1KΩ resistors. when there appears to be more resistors of a different value. What value were they? Thanks

[@ahmedsorkatti6468]

I don't get why the clock input on the chip is inverted.... can someone explain?

[@ahmedsorkatti6468]

does it actually invert the clock signal or it just denotes that the circuit triggers with the falling edge?

[@Otakutaru]

could it be possible to use the output of an edge detector to quickly update both JKs without the need to wait for the clock to go low? Is it useful in any way, apart for looking more responsive?

[@stathisgeorgiou2421]

what if I place a pulse detector between the master's sr latch and gates and the cable with goes to the inverter for the slave sr latch. Will it detect a signal only at the rising eage of the clock or it will make a racing problem again?

[@kashifahmed1525]

Sir do you mean to say that master slave jk flip flop is level triggered instead of edge triggered?

[@tusharbadgujar7550]

Can you provide the circuit diagram for clk signal used for this?

[@FBI_Master]

could you just use a debounce circuit

[@NiamorH]

very interesting

[@Neverforget71324]

Personally, I would've just put something in the circuit to slow down the feedback signal... but i understand that's not really a viable / long-term solution if you want to go up higher in clock speed.

[@kirill_bykov]

But why now first stage of master-slave JK flip-flop does not generate extra pulses as simple JK flip-flop did? That means conditions were wrong (probably bad clock pulse) and no need in second stage.

[@theonecommenter]

This flip flop quite the joker

[@colejohnson2230]

can you do a breadboard 3-output randomizor

[@SuburbanDon]

Fun stuff.

[@shubhamu3096]

Which component is used for clock.

[@lhsazevedo]

Ben, why you arent posting on Patreon too?

[@POLMAZURKA]

what is "ones catching"?

[@SuperENGLAND92]

I think you should use RC circuit again in the CLK part. If you do not use RC circuit, you may have again racing condition in the master and slave part because when CLK is high, master part will always toggle and when CLK is low, slave part will always toggle. Also, the period of CLK should be very small for example nanoseconds if you do not use RC circuit.

[@Damnesia2]

If it's connected correctly, the second one should never be able to receive both J and K inputs as 1s, so it should never be oscillating and the first one only toggles when receiving the output of the second JK in the series, so it shouldn't oscillate either

[@yoramstein]

great videos but how do we know what is "the last flip flop" ? Can you number# your videos to return.

[@bobdagamer640]

They’re in order on the playlist

[@yoramstein]

@@bobdagamer640 Thanks.

[@jonathanolson772]

Master-Slave JK flip-flop: smallbrain.jpg JK flip-flop: glowingbrain.jpg D Latch: shiningbrain.jpg SR Latch: transcendence.jpg

[@AlaesterNikolaiModern]

Isn't that backwards?

[@davadoff]

@@AlaesterNikolaiModern yeah

[@j4Naga]

Hi Ben , when are we completing 8 bit computer module

[@Ewmiter]

in about 50 vids

[@garydunken7934]

He's slowly building them one block at a time. So I guess we all have to wait patiently. Master-slave JK flip flop is just done, hopefully we don't have to wait too long for the next video about Counters.

[@j4Naga]

G Yogaraja yes. More the wait, hotter you create 😁

[@fritzerooo]

Hi. Just want to confirm. Should we need to use AND gate? Some references provided us all logic gates are NAND. Thanks for answering in advance!

[@raghavendrasaicherukuri5832]

U should use NAND gate

[@SerandibBroadcast]

How to decide what is set and what is reset?

[@SirRebrl]

If they're unlabeled, then either input could be Set or Reset. Then whichever one you call Set determines which output is Q, because it'll be the output that goes high if you take Set high, and the other output is Q-complement. The circuit is symmetrical, so it makes no difference until you connect it to other things.

[@SerandibBroadcast]

@@SirRebrl okkkk, thanks bud.

[@ropersonline]

To beat the race condition, wouldn't it also have been possible and sufficient to simply use the CLK & !CLK edge detector circuit that was shown in the D flip-flop video? There was a simple circuit shown there that split the clock signal and fed one side into an AND gate and another first through a NOT gate and then into the same AND gate. It was shown after 7m29s here: kzbin.info/www/bejne/j4iQkHqhisyog68m29s Wouldn't that also do?

[@AI_Image_Master]

Because it is not stable. I would certainly bet that one inverter would not create enough of a delay. You would need a bunch of inverters, but you can not calculate the number of inverters required. It would be trial and error, while the master/slave ff does not have a problem. If you want to use a pulse for other reasons then you really need to use a much more complicated circuit to accomplish that pulse. That is not required for this application.

[@clooskey]

That Rigol is like... *triggered*

[@TimHaloun]

So where are all the people in the comments saying you shouldn't put logic on the clock that repeated themselves endlessly against simply ANDing on the register video?

[@ilanlopez9826]

I'm kinda new to this stuff so correct me if I'm wrong. I don't think the second S-R latch portion of the circuit is needed, the outputs of the first S-R latch are the compliment of the outputs of the second latch, wouldn't it be simpler to replace that section (only the stuff surrounded by the green box green) with two not gates, or am I missing something?

[@zoltankurti]

It would keep toggling itself extremely rapidly while the clk is high.

[@oliverdowning1543]

POV: when Ur datasheet is outdated.

[@ek3200]

You SOUND LIKE LARRY PAGE!

[@masbro1901]

your JK FF is bit different with others in internet, they built all with NAND

[@davadoff]

The circuit at 5:21 doesn’t work. J can’t set Q high: the bottom AND gate will always output low because of the low input from Q. With Q & J low, the bottom NOR gate outputs high making K & the top AND gate irrelevant.

[@davadoff]

I studied JK flip flop built with all NAND gates and it looked correct

[@LordPhobos6502]

hmm... if you wanted, you could use the master-slave arrangement but only use the intermediate outputs if you wanted outputs toggling on the rising edge... just a thought! :)

[@Cherijo78]

The industry as a whole has been trying to move away from Master/Slave terminology. What would be the best alternate descriptors here, or has one been settled on yet? Primary/Secondary, Lead/Follower, some other terms?

[@coolbionicle]

are the preset and cleat the pins used to make the jump on the counter?

[@Videoswithsoarin]

im trying to make this with just NAND gates and if i look it up online and test it in logisim and on my breadboard it doesnt work, idk if its that the simulation isnt that good or if i wired it wrong on the breadboard but it doesnt work. im using cd4011be.

[@ziad4744]

there is a wrong in this scheme. you have to switch the feedback or to switch the NOR gates with NAND

[@SirRebrl]

The diagram is correct. If Q is high for instance, then the feedback to the K input-AND is high, and then if K is high and the clock is high, that takes that AND gate high, turning the first-stage Q low, which turns the first-stage Q-complement high. Then when the clock goes low, that propagates to the second stage. The feedback only enables either input when the opposite output is high, which is what gives it the toggle ability if both inputs are set high - only the input for the state opposite the latched stat goes through. You might be referring to other setups based on NAND gates and applying what you know from those? The internal logic of an AND-NOR setup is a little different than an all-NAND setup but it comes out working the same just looking at the inputs and outputs. If you draw it on a whiteboard you can step through the signal propagation by labeling the connections with 1's and 0's. That's what I do, anyway.

[@barfbot]

that flip flop is cruising to be cancelled

[@happycolours8551]

What I was thinking

[@Jirayu.Kaewprateep]

📺💬 There are more applications as you may hear about clock and Q compliment for signaling transmission. 🥺💬 I start to watch his VDO from the built computer and not remote device control or transmission I do not know which one is harder but all are interesting. 📺💬 Next, we go to the full center and binary counter.

[@rahulmaurya2668]

Sir Make a video on how to find the output waves of flip flop Please...

[@binhutibhusanrout4060]

Please give me the list of components using to make d jk master slave flip flop on breadboard

[@megri3441]

brain burner feedback chains

[@binhutibhusanrout4060]

Please give a video how to construct this master slave circuit

[@TREmreprogaming]

13 dislikes from sjws

[@zes3813]

ts not intx or uninteres

[@roi12555]

It's not PC today lol.

[@sonofmanarkjazz8965]

I don't want to jinx it, but i think someone is getting really close to figuring out how to produce free energy. Problem is, i don't think there's a way to turn It off once It starts.

[@greeger1658]

there isn't such thing as free energy

[@DigGil3]

No T-Flip Flop. I'm disappointed.

[@pareshmhatre4019]

You are talking about the different circuit, change your circuit!

[@cgarzs]

Oh my, little did we know that in the future the title of this flip flop would inexplicably become racist. 🤣🤦‍♂️

[@streetDAOC]

Racist name but hell yeah

[@TheDanielLivingston]

It’s racist? Are any of these slave circuits Black? No? Then how is it racist?

[@streetDAOC]

Daniel Livingston not nice to be racist bud

[@TheDanielLivingston]

PowerfulVeganHands Not only am I not racist; I’m anti-racist. I’ve marched for BLM. I’ve donated. I’ve canvassed. Now tell me again how the master-slave metaphor for devices is racist.

[@Ursacke]

Context matters. The terminology is not racist. But we might have to talk about the internal wiring leading up to pins 10/11 on the DM7476 connection diagram... do you see it? 👀

[@streetDAOC]

Ursacke Don’t start with me ursacke

[@YouB3anz]

Disappointed to see the master/slave terminology propagated here. The terms represent too inhumane a concept to be thrown around in such a casual setting. it's pretty cringe. Claiming that they're the best set of terms to describing what you're doing here with electrons and copper wires is very well, lacking in imagination to say the least.

[@TheDanielLivingston]

Of all the so-called “offensive” Comp Sci terminology (blacklist/whitelist, master branch, parent/child/orphan) the master/slave terminology is the only one I will support changing. It is the only one that I have seen black people taking issue with. The rest just seem to be white liberals who care about symbolic social justice victories rather than actual victories. I’m quite disgusted by those types of people.

[@maxine_q]

No sane person thinks about a literal master and a literal slave when talking about these things. At no point did he claim that they are the best set of terms, it's just what their actual name is, therefore he is using it. The only thing I've always been confused about are blacklist/whitelist; I never know which one is "good" or "bad". I would much prefer to use target/exclude instead. That way it's a lot easier to understand which one does which.

[@YouB3anz]

@@maxine_q Well, master and slave refer to very specific human relationship. The terms are quite visceral and I think it's hard to ignore them. They are unfortunately named but I was at least hoping Ben would at least address it like, "hey, these are some pretty weird names"