Memory Mapped I/O and an introduction to Serial and PCI Express Busses

[@bharathumasankar]

Very under rated video. Presenter's knowledge and passion on the subject is amazing.

[@ilirlampros]

I got what I wanted to understand about MM-I/O in the first few minutes. Hats off to you sir.

[@MarkMossberg]

Incredible. One of the best technical educational videos I've ever seen! I'm a software engineer that has been thrown into a firmware task for my project and this has been helpful for improving my foundational understanding of the domain.

[@JohnsBasement]

Thank you for your support!

[@dudeabideth4428]

Same here . I have been a storage file systems guy and now I am a fw engineer . Feels like a junior learning the basics . Such clear communication in this one .

[@kumaraswamymudide1177]

You are amazing, John. You nailed the fundaments. Great video. Would you post more videos on PCI express by talking, on enumaration, root complex design and PCI express controller etc?

[@JohnsBasement]

Thanks. I'm not prepared to look that deep into PCIe. Sorry.

[@eealec2138]

I love your style of teaching! I hope you are still making videos!

[@JohnsBasement]

Thank you! Yes, I am making more. Hopefully some will be of interest.

[@ChrisJackson-js8rd]

watching this style of presentation i miss transparencies and overhead projectors versus white boards and malformed ppt

[@EvilSapphireR]

I can’t put in words how helpful this video was. I’m a malware analyst who wants to delve into malicious bootkit analysis, for which I wanted to understand how CPU talks to its peripherals at a low level, and I came across your video which perfectly built up the knowledge from basic CPU -> Memory and I/O connection to modern day PCIe, and with perfect historical context! Without your video it would’ve taken me days to put together these concepts in my mind. Thank you so much! If you don’t mind, I have a question. To understand CPU -> peripherals connection, I was trying to understand an article that was discussing an *Intel Pentium III CPU -> PCI bus (Intel 815E northbridge chipset) -> AGP Graphics card (PCI device) communication*, and like you said at 05:24, the CPU doesn’t care about how its address buses are connected to external components in the motherboard, I’m trying to understand the boundary between CPU and the peripheral in such a case. In your initial diagram, from what I understand, the address bus -> memory/peripheral connections are hardcoded (hardware soldered?) on the motherboard. Therefore you have specific hardcoded memory ranges to access the different memory/IO chips which would probably come in the datasheet of the entire board (which could qualify the entire setup as a microcontroller?). But in case of the Pentium 3 or any modern day CPU, it is the firmware (BIOS) inside the flash ROM of the motherboard that allocates different CPU addressable ranges(System Address Map) to different memory/IO chips. And the BIOS does this mapping by setting the Base Address Registers (BAR) of the PCI bus to proper values. The BARs are accessed via port mapped I/O (Intel IN/OUT instructions). How can the CPU directly talk to the PCI BARs with the port mapped I/O instructions? Are the CPU address buses soldered onto every motherboard in such a way that no matter the CPU, Chipset, the port mapped I/O on specific addresses will always target the specified PCI BARs, and the reset vector will always target the ROM (which in my mind would have to be hardcoded as well, since the first instruction of BIOS is fetched from the ROM when the PCI chipset hasn't even been initialized)? And does that make PCI (or PCIe) the specification every MOTHERBOARD vendor should follow (not the individual CPU or any chip vendor, although I see why a PCI endpoint vendor would have to follow PCI compliance as well), since in my mind motherboard vendors are the ones who are actually connecting the different chips together. Is the Intel 815E chipset the PCI Bus in my example, since the article says it is the chip that does all the CPU->peripheral address routing. I'm just trying to grasp the big picture, I hope the text wasn't too cumbersome to read. :)

[@JohnsBasement]

Sorry for the delay. I just noticed this posting today. The short of it. Is that the bios boot ROM and the control units for things like the PCI and PCI Express systems are going to be hardwired on the motherboard to known addresses on the CPU bus. Then when the boot ROM and/or the OS start running, they will tell the controllers what range of addresses to react to/open up/map to each of the cards in the PCI slots.

[@wayne8863]

World class, top level explanation on PCIe. ❤it!

[@JohnsBasement]

Thank you!

[@berlin-unlocked]

galactically great video!!! Extremely clear even for a programmer who learned 1 course about gates and wares 10 years ago

[@JohnsBasement]

Thanks!

[@Slojammed]

You're like the AvE of electronics. Great video!

[@JohnsBasement]

@@Slojammed I had to google that. Looks interesting! Thanks!

[@JC-jw2kw]

Amazing ! First class video

[@rajeshsaha3446]

Awesome and very practical session it is; learn lots from it

[@JohnsBasement]

thanks!

[@benravin6547]

Does that mean if the data bus is of width 32 bit, then shift register also to be 32 bit, right? What ever the data bus width the shift register also to be of same length?

[@JohnsBasement]

@@benravin6547 not if you synchronize the reloading of it each time it is emptied. Normally a FIFO is built into such serializer/deserializer (aka serdes) interfaces so that the parallel interface can be narrower than the total message size. It is then up to the DMA or CPU to keep the FIFO(s) from overflowing.

[@benravin6547]

Thanks John. When PCIe is used it is connected to CPU through which bus. If the data bus is 32bit, how the data is passed to root complex, for example on Arm kind of cpu?

[@JohnsBasement]

@@benravin6547 The physical data bus in a modern PC is usually wider than the word length. How the PCIe lanes are connected to it differs from CPU to CPU.. which is part of why one might be preferable to another. You will have to consult more detailed documentation of an actual CPU design to see how it works.

[@Int3rSys]

amazing and very informative. thanks!!

[@Zjk580]

is a decoder an multiplexer the same thing?

[@JohnsBasement]

With respect to basic digital logic circuits, a decoder with an enable input is a demultiplexer.

[@dudeabideth4428]

Gosh I want you as my teacher !!

[@kevindurant5296]

Best video ever seen👍👍

[@JohnsBasement]

Best review ever seen! 😀

[@zhaosinicholas921]

Gem! very informative

[@JohnsBasement]

@@zhaosinicholas921 thanks! Glad you liked it.

[@maksimtochilkin8090]

Amazing video, thank you!

[@JohnsBasement]

Than you for saying!

[@dbharathi2003]

Thanks so much. Was very useful

[@JohnsBasement]

You're welcome!

[@雷东宝-s6t]

I watch your video ,because I reading "xhci spec " I wish your video can help me understand the xhci

[@aceqbaceq777]

thank you Sir! very clear !!

[@JohnsBasement]

You're welcome

[@ChrisJackson-js8rd]

to be honest i think you could have taken the serial manifesto even further. the fundamental differences how humans experience time as compared to other spatial dimensions make segmentation of data cheaper and easier, which in turn allows for greater information density in serially encoded data as proved by einstein in his theory of general clock skew 🤣

[@JohnsBasement]

@@ChrisJackson-js8rd 🤔