Hi , At signal routing stage , during Global routing whether the entire design (CTS completed design) is divided into G-cells or only the availlable routing area?
@jairamgouda2 жыл бұрын
Entire design
@naveensilveri13863 жыл бұрын
Very good concept about routing layers
@shaikhaseena73802 жыл бұрын
Make a video how we can calculate pitch offer and spacing between metal layers
@13_jayantkumar782 жыл бұрын
How you are saying that Lower metal layer offer high capacitance and Higher metal layer offer less resistance? Please give explaination on that
@RamaKrishna-kp7fk2 жыл бұрын
Very good concepts 🔥🔥
@bindhur52773 жыл бұрын
Thank you for the video!! Great visual representation and explanation!!
@ujjawalagrawal51952 жыл бұрын
Great Video Sir !!!
@jairamgouda2 жыл бұрын
Thank you
@RamaKrishna-kp7fk2 жыл бұрын
Sir i have some questions related to pd..how to reach you to get answers..ur explanation are 🔥🔥🔥
@jairamgouda2 жыл бұрын
You can mail me
@tamilselvanselvaraj17982 жыл бұрын
Nice
@sardharvankunavath19882 жыл бұрын
if we connect metal1 ,metal2 and metal3 can u compare their resistivity ??/
@jairamgouda2 жыл бұрын
Can you please be a little more specific? I didn't probably get you properly. Do you mean what happens to the total resistance if we use multiple metal layers for a net? Or do you want me to brief about the magnitude of change in resistivity as we go for higher layers?
@sardharvankunavath19882 жыл бұрын
@@jairamgouda actually my question if M1 upon M2 like that if we connect what will be the resistivity will varry and which metal have more resistivity and why ??
@jairamgouda2 жыл бұрын
@@sardharvankunavath1988 Yes, I got you. Basically as I have explained in the video, the resistance of the metal M0 is the highest in metal layers and the capacitance is the lowest. Similarly the highest metal used in the chip maybe m5 or M10 or M 18, whatever it is, wil have the highest capacitance and lowest resistance. Why? Because the width of the metals usually increases as we go from M0, M1 to top metal in the design.