Metal Layer basics in VLSI

  Рет қаралды 10,586

Jairam Gouda

Jairam Gouda

Күн бұрын

Пікірлер: 17
@zunaid4664
@zunaid4664 2 жыл бұрын
Hi , At signal routing stage , during Global routing whether the entire design (CTS completed design) is divided into G-cells or only the availlable routing area?
@jairamgouda
@jairamgouda 2 жыл бұрын
Entire design
@naveensilveri1386
@naveensilveri1386 3 жыл бұрын
Very good concept about routing layers
@shaikhaseena7380
@shaikhaseena7380 2 жыл бұрын
Make a video how we can calculate pitch offer and spacing between metal layers
@13_jayantkumar78
@13_jayantkumar78 2 жыл бұрын
How you are saying that Lower metal layer offer high capacitance and Higher metal layer offer less resistance? Please give explaination on that
@RamaKrishna-kp7fk
@RamaKrishna-kp7fk 2 жыл бұрын
Very good concepts 🔥🔥
@bindhur5277
@bindhur5277 3 жыл бұрын
Thank you for the video!! Great visual representation and explanation!!
@ujjawalagrawal5195
@ujjawalagrawal5195 2 жыл бұрын
Great Video Sir !!!
@jairamgouda
@jairamgouda 2 жыл бұрын
Thank you
@RamaKrishna-kp7fk
@RamaKrishna-kp7fk 2 жыл бұрын
Sir i have some questions related to pd..how to reach you to get answers..ur explanation are 🔥🔥🔥
@jairamgouda
@jairamgouda 2 жыл бұрын
You can mail me
@tamilselvanselvaraj1798
@tamilselvanselvaraj1798 2 жыл бұрын
Nice
@sardharvankunavath1988
@sardharvankunavath1988 2 жыл бұрын
if we connect metal1 ,metal2 and metal3 can u compare their resistivity ??/
@jairamgouda
@jairamgouda 2 жыл бұрын
Can you please be a little more specific? I didn't probably get you properly. Do you mean what happens to the total resistance if we use multiple metal layers for a net? Or do you want me to brief about the magnitude of change in resistivity as we go for higher layers?
@sardharvankunavath1988
@sardharvankunavath1988 2 жыл бұрын
@@jairamgouda actually my question if M1 upon M2 like that if we connect what will be the resistivity will varry and which metal have more resistivity and why ??
@jairamgouda
@jairamgouda 2 жыл бұрын
@@sardharvankunavath1988 Yes, I got you. Basically as I have explained in the video, the resistance of the metal M0 is the highest in metal layers and the capacitance is the lowest. Similarly the highest metal used in the chip maybe m5 or M10 or M 18, whatever it is, wil have the highest capacitance and lowest resistance. Why? Because the width of the metals usually increases as we go from M0, M1 to top metal in the design.
@sardharvankunavath1988
@sardharvankunavath1988 2 жыл бұрын
@@jairamgouda okay tqs for ur valuable response
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