NCOs are everywhere - here's how to make one using an FPGA

Numerically Controlled Oscillators (NCOs) give FPGA designers an easy, flexible and efficient way to generate sinusoidal signals of arbitrary frequency. In this video, we show how an NCO works, how to design one for a particular output frequency. We then do a demonstration using Quartus, Verilog, the Cyclone V starter kit and a 14-bit DAC.

[@duncandewaal7022]

One of the best explanations I have seen thus far. Good job.

[@joelstyer5792]

This was a very good explanation, very clear and concise for anyone familiar with Quartus. I've been using Altera (now Intel) parts since the late 1980s (with A Plus and later Max Plus then Quartus). For anyone else watching, yeah, it really is that simple to add a PLL which I tend to do for most designs. I have only rolled my own NCO with DPRAM Lookup tables (to change the output waveform) but found this very interesting to watch. Looking forward to other Intel FPGA videos.

[@miladaslanian]

Hello. It was great. Is it possible to send us a video about vivado or vitis and explain about NCO?

[@andrewphillip8432]

I’m interested in learning FPGA. Is the cyclone V kit a good way to start? I haven’t done much research yet but I hope to run similar algorithms to what you have shown on this channel, especially FFT.

[@navneetsingh5529]

Which version of quarts prime do u use, pro or standard?

[@kevinamonteverde]

Hi... Thanks so much for this video. I'm using FPGAS for the first time and this is super useful for my research work... One question: Is there a way to control the frequency/phase in real time? Here i see it's hardcoded, I think.

[@jrstf]

I would expect the 8 bit resolution of the picoscope to produce the harmonics you were seeing along with all that noise.

[@tiagoogionicostalonga7777]

Thanks a lot for this great explanation! It helped me a lot in my research... I have just one question... whats is the maximum output frequency i can set up in NCO? It depends on my FPGA?

[@VisualElectric_]

It will depend on the clock frequency. In a mid-range FPGA, you could set the clock at 100-200 MHz and then output a 10-20 MHz sinusoidal wave with 10 samples per period (reasonable quality). If you push too high, the waveform starts to look like a staircase, but theoretically, you could go right up to Nyquist.

[@tiagoogionicostalonga7777]

@@VisualElectric_ Thank you... just one more question... how to set up the amplitude of the wave?

[@jrstf]

@@tiagoogionicostalonga7777 - External linear amplifier, with DC offset adjustment, if you can. Doing it in the digital domain reduces the resolution of the DAC and you still need to add in a DC offset to remove the DC component which you presumably can't do digitally.

[@michaelpierce3264]

interesting that the alpha Juno oscillators are based on this

[@noel101082]

Are you from Newport by any chance?

[@VisualElectric_]

No, but I am from Wales

[@noel101082]

@@VisualElectric_ u actually sound like amate of mine from cwmbran but i always thought he sounded like he was from zooport. used to have a recording studio in Blaina.

[@satviksharma3722]

EPIC!!!

[@hightlightlol2106]

have you ever tried feed output of ADC to input of DAC on the same ADA board? I tried it but got notthin! Just simple that I connect the output of ADC to input of DAC to observe the S21 of the system, it should return the same input as the output but I got notthing at the output. The modes are set correctly on both ADC and DAC, they used the same master clk It will be great if you give me an email, I would like to ask you some questions

[@VisualElectric_]

I've done this many times. The usual suspect is the wrong pin assignments. I cracked it in the beginning by using the example that comes with the THDB-ADA board.

[@hightlightlol2106]

@@VisualElectric_ I have done this too, I cracked the example, turned out that the powerdown funct pin needed to set to 1 to get them work!