Preset and Clear Inputs in Flip Flop

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@@bhargavpratimsharma2024 what did you want to say?😂

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@@PriyanshuSharma-ey3bc exactly lol

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Make India Great Again🇮🇳

[@pratikaggrawal2172]

Thanks a lot. I appeared in gate in 2017 and lost the notes. Now EEE is my optional in CSE. Thanks for make me remember the concepts easily.

[@_ash_ish_]

What happened to you cse bro?

[@ericwright3382]

Thank you for the video. Although not common, there are times when both preset and clear are brought low at the same time. This IS defined as Qn and /Qn both outputting HIGH. While using spare gates, a flip flop may be used as an inverter by tieing D, CLK, and CLR to low, and any signal on PRESET will end up inverted on Qn. -try if you ever need one inversion before using the second flip flop of a 74xx74.

[@GOURABCHAKRABORTY10287]

you are doing great work sir! keep it up..... much respect!

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your videos are very precise and nice

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Much love and appreciation from Tanzania 🙏🏽🙏🏽🙏🏽🙏🏽

[@ManishYadav-gx8ce]

Regarding active high and active low confusion, think in terms of High and Low instead of 1 and 0. In active low logic(0=High and 1=Low),and in active high(1=High,0=Low).Active high circuit implies circuit is functional only when input is 1. Similarly, Active low circuit implies circuit is functional only when input is 0. Here, preset and clear are active low, meaning preset will be high(functional when we have 0 input in it), and will set Qn=1. And if clear is also 0(here high), it will again try to reset Qn, i.e. will try to make Qn=0. So this(Preset,clear=0,0) is not used. While Preset=1(low), it will be non functional,same impiles for clear.

[@prithvisinghmann8506]

Thanks a lot bro! That was a pretty good explanation. You helped me remove whatever doubts I was having :)

[@D.KrishnaPriya]

very clear explanation thanks bro

[@subhajitkayal9750]

Sir You are the best lectures, I have ever seen in my life. Sir please continue this chanel and keep help us.

[@ayushgemini]

Yes as mentioned in comments. The circuit diagram used in video is INCORRECT. Just google it you will find correct diagram or atleast something from where you can approach further...

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[@theabundment]

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[@akashkadambi3732]

I think it would be better for me to drop out from my college.......................Idiotic system when we can learn such high quality content for free ,then just think what the quality of education should be in the colleges........😡😡😡😡

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I also feel the same thing sometimes....😂😢😅

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Drop out ho gaye kya

[@abdulmagedkhaled9480]

man, u r the god of elctronic for me, keep it up bro, ur videos are very useful, please don't you stop uploading video, thank you very much

[@ShubhamSharma-hx4df]

Amazing explanation sir 😊

[@kishanbaranwal8331]

if clear is 0 than Qn' is 1 but Qn is not necessarily 0 because it depend on S (think if S =1 and clk =1) .Sir please clear my doubt

[@enderhawk134]

Setting the clear to 0 and the preset to 1 (or vice versa) changes the circuit so that it only has one "stable" state. It can momentarily give Q = Qbar = 1 as output, but only when clk = 1 and S = 1 (or R = 1 for preset = 0, clear = 1), which it usually will not. (I put "stable" in quotes because technically having clk set to 1 is possible, but it's just not how you're supposed to use the circuit.) [Disclaimer: I'm just an undergrad struggle through this shit with the rest of y'all. I could very well be wrong.]

[@MuskaanBaveja]

You're a lifesaver. Thanks!

[@husseinalmansory7370]

YOU ARE THE BEST MAN

[@abhishekshinde9209]

what about when r=0 and preset is 0 then qn complement will be 1 and qn will also be 1

[@taher786...]

really good explanation

[@chhavisi]

Very helpful sir

[@CuongNguyen-id1ob]

I understand that: When Clr = 0 then not-Q is directly 1. However from this point, not-Q is fed back to the upper NAND gate where Pr = 1 then 1 AND 1 is 1, so the output of the upper NAND gate (Q) is not directly 0 but dependent on the front NAND gate's output where S and Clk are inputs. Can u please explain how we get directly Q = 0 when Clr = 0? Thank you

[@wantAniket84]

I also had same doubt it will depends on s if clk is present ..

[@sepehrgolestanian6161]

I am having the same doubt

[@HelloWorld40408]

Thank You Sir

[@devashishgupta5584]

always watch neso videos on 2x

[@sushilronghe2241]

for s=0, R=1, Clk=1,Pr=0,CLR=1, both outputs will be 1, is it right?..it means it will depend upon input and clock status too..please explain

[@hari8568]

Sir how u get such depth knowledge,from just reading book I can't get so much understand in like you do in your video s ,pls reply your secret sir

[@electro-summarygate1894]

coz NESO is NESO..........

[@tiyashadas5247]

Can u please upload a video on presettable programmable counters and also down counting in asynchronous counters from any value

[@Super-_-GameR]

good work in explaining this, you are better than my doctor. keep up the good work :)

[@snehalmhaskey7722]

your videos are very precise and nice ... it is very useful to clear the concepts thank you sir

[@yusufmoallim4667]

So set and reset can be used only when the clock is 0. If not, please explain how clear is setting Q to 0 while the CLK and S are 1.

[@batikanboraormanci7954]

dude just focus on the nand sr latch on the very right... if one of the NAND's inputs is 0, the output will definitely be 1. So.. Where's the "clock" in this equation.. Nowhere... Hope you got it.

[@momentodebruh7300]

@@batikanboraormanci7954 but what if in top right nand gate, preset is 1 CLR 0 ,so two inputs of the nand gate are 1. The third input HAS to be 1 so clock input HAS to be 0. Therefore clk 0 is necessary I guess

[@batikanboraormanci7954]

@@momentodebruh7300 if preset is 1, it is the same as no preset existing at all. It wont change the way the system works a bit. If clear is 0, then no matter the clock or anything, the nand gate on the right bottom corner will be 1. So if the preset is one, then its already not changing anything, the ff will function normally on that side. The clock's impact will be same as expected. if clear is 0, as QNcomplement becomes 1, Rule 1 : you dont turn both preset and clear to 0 at the same time, that just breaks the system, so preset stays 1 2: if set and clock are also on, QN will be 1, meaning that the ff is misfunctioning, because you tried to "set" and "clear" at the same time. With or without the clock, the S will be the one breaking the system So the statement "clock has to be 0" is wrong Right is " s and clear dont work together, logically or practically"

[@momentodebruh7300]

@@batikanboraormanci7954 cool thanks

[@yannis3756]

That is correct, Clock has to be zero. There is a misconception in the above video and it precisely has to do with the clock signal. First i think we can all agree that: If SET is 1 and CLK is also 1 then the output of the TOP LEFT NAND gate is 0, which is also one of the 3 inputs of the TOP RIGHT NAND gate ------> If one input of a NAND gate is zero then its output Q, will always be 1, no matter what the other inputs are doing. So for the SR FF shown in the video above, during the time SET is 1 and CLK is also 1, the SR FF cannot be cleared ! Note: we are ofcourse assuming CLK is a proper 50% dutty cycle ON, 50% dutty cylce OFF traditional clock, just like all clocks. So for the SR FF in the video, as it is drawn, CLR and PRST are not Asynchronous, because of the 50% ON clock duration. For CLR and PRST to be trully Asynchronous, the SR FF MUST be EDGE TRIGGERED ! (In this case Positive edge triggered) That way when the "clk" input to the FF is pulsed (from 0 to 1), it will immediately return back to 0 instead of staying at 1 for 50% of the clock period. But the edge triggering circuit is not mentioned in the video... This is the critical detail the lecturer forgets to mention : /

[@lehaswinipalla3365]

Can't thank you enough

[@RaviKumar-cd5ff]

everything is perfect sir.

[@averytijerina3382]

I was confused when we made the truth table. I understand the way the preset and clear inputs are effecting the circuit, but I think we switch our analysis from the blk diagram and the circuit at the same time, because when preset is 0, it is inverted on the blk diagram so it is a 1, and it doesn't effect the NAND gate. in the same way, when clear is 0, it is inverted to a 1, and so that would also not effect the NAND gate. If i looked at it in this way, that would make the truth table backwards. I hope someone could clarify this mix up.

[@boutrikmohamed3082]

actually i have the same confusion right now any explication for me pls?

[@ganeshmula4508]

SIR, Truth table which is taught in this video is correct in two cases 1)either clock =0 2)or R & S =0 I am thinking in this way frnds. Pls correct me if I wrong

[@powarito1337]

Thank you so much for the video. Bu what about Master-Slave triggers? I saw that you need to put Preset and Clear both in Master and a Slave. Why can't we just put them only in Slave, which gives as true Q and nQ outputs?

[@Andrei-ds8qv]

You have very good videos, Sir, ,thanks!

[@Chrisymcmb]

When "Not Used" is mentioned, it means we literally want to avoid those kinds of signals on such circuits or else they would result in unprecedented outputs right?

[@HBFortunato]

can anybody help me? in this video, the teacher shows the block as active low and the table is for active low right? then how about active high? where preset and clear doesnt have bubble? what is the values on the table?

[@beinglulu3681]

well explained, thank you

[@evanaw1164]

I have a Question. Above, it was said that when Preset = 1 and Clear = 0, Q' will be 1 and Q = 0. However if i set S = 1 and CLK = 1, i would get 1 for the Q ( because the inputs are : 1(Preset), 0(NAND of S(1) and CLK(1)), 1(Q') ). Are you implying that the inputs are actually neglected ?? Anyone care to explain?

[@yueyu-md1vo]

i have the some question

[@rajeev-p4d]

thank you sir

[@ElectronicsByVartul]

When Pr=1, Clr=0, Qn(bar)=1. But how Qn goes to 0? As, NAND gate has 3 inpus. For Qn to be 0, all these inputs must be 1. Qn(bar)=1, Pr=1, what about the 3rd input(middle one)? How you can ensure that this is always 1? Please explain

[@sxl109220]

Vartul Sharma i have the same question with you. Plz someone answer this question. Why q and qbar should be always complementary?

[@sarthaksuper284]

well preset and clear are used to set state when circuit is just switched on so no input is considered from the prevois part and so only 2 ones are required to make q bar zero so in simple terms clock is 0 when preset and clear are used

[@ashishrawat8069]

@@sarthaksuper284 Nice Sarthak you help in my doubt clearification

[@arindampal2796]

how can you assume q and q bar will be complement of each other when u set clr or preset at 0, without knowing the value of S and R? plz clear this confusion.

[@sarthaksuper284]

arindam pal clock is 0 when preset and clear are used that is circuit is in inhibited state.... because it is used to set value when power is just turned on

[@nihadabbikar5788]

What's the use of present and clear and why they are operated active low???? Plzz reply

[@baswarajsghali2074]

By using preset and clear we can make flip-flops set to 0 or 1

[@Nomadicvib3]

i have a doubt.in practical experiments,how do we connect preset and clear to ic chips in a bread board

[@giack6235]

it's not so clear how could be that if we have Preset = 0 (with Clear = 1) we have Qnot = 0 in every case. It's not possibile if lowermost input of latch is 0, because in that case we have Q = notQ = 1, which is an invalid state. Is it possible that Preset works only when clock is low? because in that case it could be...Thank you

[@ganeshmula4508]

I have also got same doubt

[@karanvishwakarma8028]

Thank a lot sir it helped me a lot

[@bhagiallala8897]

Can you please explain the active low and active high outputs of s and r ff and CLR=1 and PRE=1. At that condition how it will work

[@SoOWhEn]

Question: from the block diagram, isnt it that when clear =1, Qn=0 and when Preset =1, Qn=1? because for the block diagram there is an inverter attached, so when clear =1, the circuit is actually getting 0, making Qn=0?

[@hassanalshehri6855]

***** If we are not taking the complement of preset, how do we get (preset = 0 => Qn = 1)? We need to look at the the output of (S'+clk') to determine Qn, right? Also, I'm a bit confused about the active low input, if you have a video explains this concept please provide me with its link in the comments box. Thank you!

[@sravyamiryala9194]

i gone through u r videos amazing,but preset=0 and clear=0 in nor gate entire thing changes once explain it

[@aravindkumar3101]

It's total confusing can anyone explain it briefly.... pls

[@akrammohammad1569]

THANK YOU SO MUCH

[@ayushgemini]

1) Bring a connection from preset, give it at 2nd i/p NAND gate on LHS. 2) Bring a connection from clear, give oy at 1st i/p NAND gate on LHS. NOW THE CIRCUIT IS CORRECT...

[@sagarheralagi7199]

In some circuits clk is bubbled and in some ckt clk is not bubbled is there any logic reason ?

[@raphaeljs7239]

Bubbling usually indicates the use of a not gate or inverter

[@shouryavermaelex19kanpur7]

What is the difference between Clear and clear baar

[@saisumukhakv8153]

when u make clear=0 qbar becomes 1. preset is obviously 1 when clear=0. so q will become 0 only if the output of s and clk nand gate is also 1, because output of nand gate is 0 only if all inputs are 1. but how are you sure that the output of s and clk nand gate is always 1. what if i'm trying to set the output when clk is high???

[@anveshikaagrawal6296]

Sir, Slease upload the videos for asynchronous sequential circuits

[@meghanmamillapalli1317]

Sir,How Qn will be 1 for prst=0 and clr=1 for clk=1 & R=1.

[@roatt.tilma1]

When clear is 0, Qn_bar is 1 but for Qn to be 0 at this time S should be 0, so how is it independent?

[@mayuripawar5467]

Sir...as u said that In block diagram it is low active pins ...means if we give PR =1 & CLR =1 than ultimately the input to FF is 0 & 0..... and then it is condition of not used...... Then how it is possible..... Sir I'm in confusion .... Plz clear the doubt....😊 Thanks

[@whyutpal]

since both preset and clear are active low inputs, if they are high then they won't get activated and hence the flip-flop will work in a synchronous fashion. Synchronous means that input data will be tranferred to the flip-flop output only on the trigerring edges of the clock pulses. when PR=0, preset pin will get activated and output will become HIGH and when CLR=0, output will be zero and hence flip-flop will work asynchrously. Asynchronous means that any of the asynchronous inputs(PR,CLR) can affect the state of the flip=flop independent of the clock. Hope your doubt is cleared.

[@amandamedevil158]

I don't understand what is meant by "active low" , would you pls show me where did u explain it!? Cause I'm focusing only on sequential circuits in this semester . And how to make a timing graph too ! With showing the difference between FF in it ♥ Sure I must thank you so much for your efforts , you do help me to understand more than my lectures do 💪👏

[@sashankmachiraju2466]

Active low means that when the input is 0 the circuit works. Active high, which is the generally used condition, is when the circuit works on the input 1

[@MohamedMagdy-lm3vm]

what's different between sync and Async inputs ?

[@muhammadmuneebkhanafridi154]

You said it wrong at 3:35. We will consider it as active high, because if we will take it as active low(in your case), then we have to revert the given values. Active low : (PRE)' (CLR)' Active High: PRE CLR won't it ?

[@suketsisodia4076]

truth table will be same for NOR gate?

[@AbdullahWL]

big thanks

[@wunnatinoo3039]

Is the preset and reset same as the set and reset???

[@Ebuilt]

Do you have Lectures about Trafic Light etc???

[@vamsikrishna5391]

hii sir, sir do memory cards also have flipflops i.e d flipflops inside but if we remove power supply Vcc how do a d flipflop stores the data becoz in practical case we remove memory cards n pendrives but it still holds data how does this stuff works.

[@yashkaranje98]

Sorry, but I'm not so much cleared about preset and clear from this video. I want to know about its applications, and why do we use them along with how does it work actually. Will you please let me know by creating a video for this shortly?

[@shashanksingh4692]

can we also use reset in the place of clear?

[@manikanta5002]

Hiii Neso academy your lectures are quiet good. I have problem in understanding in STATIC Timing Analysis(STA).Can you please make a video on that topic

[@royaleducation3015]

hello..sir can you please upload the lectures for HDL implementation of digitat electronics

[@exol_ruchan]

THANK UUUUUUUUUU SIR

[@binitamalik8386]

Clear 1 must give Q=0 right?

[@kumarbinay999]

sir which one is lecture no 121??? one after the clock lecture......

[@prakharsrivastava7129]

Can u please explain the 0 1 state again in more detail ........relating the clear=1 as an input ?

[@RitayanMitraggmu]

what about the preset and clear in case of JK flipflop?? because u have only shown for SR flipflop!

[@satyakrishnavinjamuri1706]

It has the same effect.

[@ramprakashvel]

It just do the same as in SR flip flop. when preset=0,Q=1&Q'=0 and when clear=0,Q=0&Q'=1 As we infer from the diagram it does not depend on the S and R value as well as J and K value

[@davidstern1699]

how does clear being equal to zero affect Qn. I see that it would force Q'n to 1 but not how it would do anything to Qn.

[@ANUSHKASINGHBEC]

because Q'n is complement of Qn . Which will set it to 0 as it's complement is 1.

[@sxl109220]

ANUSHKA SINGH 15BEC0306 why q & q bar should be complememtary?

[@adarshpandey3149]

u r best...

[@sepehrgolestanian6161]

what if clear=0, and preset=S=Clk=1? I think both outputs will be 1 in this condition.

[@averytijerina3382]

Oh I messed up on my truth table for tha NAND gate. thanks

[@vidhucatherineantony]

How can you put preset and clear in a NOR latch...

[@akarshchaturvedi2803]

AND AND NOT

[@hsnazk8044]

anyone knows how to construct clear using circuitverse?

[@Mercio2]

Thank you!

[@gardedesombres3254]

I didn't understand what happens when preset = 0 and clear =0 ? can u please explaint it shortly in the comment ? Thanks

[@giack6235]

in that case we force as output of nand gates both 1, which is an invalid state

[@RichyRich18]

sir please tell us how to access these notes

[@alterguy4327]

Doubt Cleared 😅

[@lounes9777]

That's what I call an explanation, not that difficulttttttttt !!!!!!! ghhghghg certain prof are terribleeee

[@kaustubh1581]

Isn't this a latch??

[@sagarpant6026]

what if preset is 1 and clear is 0 and S =1 clk =1 ,,,, as clear =0 Qn' =1 and as clk = s =1 hence Qn=1 . So contradiction is Qn=1 and Qn'=1.

[@hamzamubashir938]

Yes I am caught up in the same thing did you find an answer to this question? Please will be very thankful

[@jaspreetpannu7854]

Thanku sir

[@svmchop]

I am not clear as how NAND gate is having 3 inputs??

[@ceasazee6649]

sir why we call them preset and Clea r

[@paritoshkumar3452]

thanks a lottttt

[@rahulbhaskar474]

I get it sir😎

[@abuzarmahmood96]

I think that when preset= 1and clear= 0 then Q should = S

[@deveeshmusic5045]

Do you go to college?

[@siddharthsinghkiryal2082]

I got the same ans

[@Ebuilt]

Lecture Number ???? plz

[@Ebuilt]

Thanx

[@roshanijaz1]

everything was going good until you wrote that block diagram according to you if pre =0 then Qn =1 but bubble of the block diagram will make pre =1 and how qn =1 HOW? and we know in nand gate the if any one input is low then output is high then how pre =1 will make output =1????????????????????

[@akarshchaturvedi2803]

The bubble isn't a NOT gate, it is just there to represent the kind of input that makes it active.

[@roshanijaz1]

@@akarshchaturvedi2803 ya actually real confusion was that there wasn't a bar over PRESET and CLR