Voltage-Divider Bias Configuration of JFET

[@johnsean2022]

very well explained sir but pls provide some question and solution also pls sir it will be helpful

[@merylldiola46]

sir thanks for this! please keep on making videos!

[@pavankalyanp5467]

Sir point on x-axis is (Vg,0) but not (0,Vg)

[@saniaayoub9534]

Right!

[@sbsonlineclasses5963]

sir your teaching way is outstanding i totally understood your lecture 100%.....thank u

[@riseabovehate9476]

But he never answers our doubts

[@mulchandparmani1666]

Complete the series Neso ACADEMY

[@sakibulislam2430]

bhai you're a gift

[@prabhugopal3]

Simply explained thanks

[@saranshgupta9119]

Sir plzz complete the entire analog series 🙏🙏

[@bilyaminuardojulde8248]

Nice and perfect

[@navjotsharma1654]

Sir love you. You r awesome

[@PubuduDissanayaka-zm9oq]

Thank you sir

[@017brajkishorsingh6]

Please correct your mistake in JFET voltage divider configuration at 12:42.one of the co ordinates of load line is mentioned as(0, Vg) instead of (Vg, 0).

[@Ankit-no6hi]

Sir thank you soo much Your videos are so helpful but sir please provide some examples and their solutions ... It will be more helpful....

[@jittebello1530]

Is there some way to solve for q-points without using graphical approach?

[@techstudent351]

Your clarification is good but, Please share notes of this !

[@Buranku-go3wu]

3:54 still if there is resistor between them the voltage of Vg will same since no voltage drop will be between them !!! correct me If I am wrong

[@ABHISHEKKUMAR-.]

Sir on increasing resistance the whole term will decrease but due to the negative sign slope will increases??? And hence it shifts towards y axis ?????

[@teralabharathkumar9349]

tq

[@savitakumari3683]

sir how you apply kirchoff's law . plzzz make one video to show it . i know it but cant able to apply here .signs problem .plzzzzzz sir explain this

[@bubunmazumder]

exactly where did u face the prob?was it to determine Vgs?is that so,then u probably did something wrong in ur calculation..check it once again..if the prob still persists then let me know..

[@umairzafar9161]

i m also facing problem in applying KVL here...can u guide me meghjit mazmuder....from where i should consult??????????

[@divyanshudhawan]

I think you are wrong because r1 and r2 are in parallel because if it is in series it will act as an individual strand and it would give no effect on the circuit. If I am wrong please correct me.

[@nitin-b]

sir, in some books operation point mentioned on drain characteristic by calculating Id and Vds. is it correct to calculate o.p on transfer characteristic? reply me soon.

[@daryentanwir9091]

No.... transfer characteristics is relation between output and input...therefore idss and Vgs should there...

[@kamleshnehra407]

Sir what works coupling capacitors ,and if i want more volume from my speaker then what will be the circuit diagram ,i mean where i have to add my speaker for FET

[@jay-rm.ballon2824]

are still creating videos to continue analog semiconductor?

[@mayeyemayeye3403]

May be we have the range of vp and IDSS HOW we can find the range Q-point

[@manshamsul2156]

Thank you mister... I have a question.. How to calculate when the circuit given has a Rs1 and Rs2 like beside it? Can you help me mister??

[@minj7194]

hai.. arent jfet suppose to be negative bias applied to the Gate. can you help me clarify on this matter.

[@jush0082]

Do you have AC analysis of this configuration?

[@gopalgowda8804]

What is the use of bypass capacitor

[@AndrewKiethBoggs]

In the case of BJT amplifiers, for gain/temperature stability a resistor was added to the emitter, RE. The addition of RE helped with the stability of the amplifier, but decreased the overall gain, Av, of the circuit when doing the AC analysis. So to avoid this, a bypass was added so that the circuit DC biasing was more stable, but in the AC domain the AC would simply "Bypass" this resistance. However, MOSFETs/JFETs are more stable than BJTs, so in this situation, I am not 100% sure.

[@uzmaghare2310]

How will Id will remain constant in this bias?

[@nitheesh4841]

why there is two equation for Id. one is linear and other eqn is non linear

[@lahatditopwedetv2111]

How about it's voltage gain??

[@manjitsingh6168]

sir 0,vgs shouldreplace vgs,0

[@-ASaiseetharamaiahPayyavula]

Very small mistake it is not (0,Vg) it is (Vg, 0)

[@evergreeneducation2230]

how the coupling capacitor is open circuited in case of DC analysis...how it happen...and when it's open circuited we remove it how this happens ...plz help.

[@umairzafar9161]

because capacitor simply block DC current....so when we deal with DC analysis capacitors can be treated as open circuit

[@AndrewKiethBoggs]

Think of the equation used to calculate the reactance of the capacitor: Xc = j/(2*pi*f*C). In DC, frequency is 0. So, Xc = j/0 = infinity, which is an open circuit. This is why it blocks DC and allows AC to "Bypass" through the capacitor.

[@azkanaseem4796]

I didn't understand how u have plot the graph kindly let me understand it plz

[@ManishKumar-tk1sc]

download this book www.rtna.ac.th/departments/elect/Data/EE304/Electronic%2011th.pdf

[@umairzafar9161]

take lectures in sequence...u will have fun surely

[@umairzafar9161]

yeah this book is awesome

[@anshuabhipsasahoo4504]

Sir what is Vs and Vd

[@ManishKumar-tk1sc]

SIR PLS UPLOAD THE LEFT TOPICS OF FET BIASING AND OP AMP ,OSCILLATOR

[@rajasripanja9053]

sir please upload the network theorem(thevinen, nortan, and superposition theorem.) please please.

[@rishabhsisodiya877]

But sir (-1/Rs) increases therefore slope also increases

[@AJAYKUMAR-vz6ut]

Why use