One hot vs binary encoding || which one is better for FPGA/ASIC? || Explained with example

Hey guys I have discussed about one hot vs binary encoding with example .
Thanks for watching.
Please do subscribe it will help me a lot 🙏

[@omganeshchoas9097]

nice bro u came back you explaining the concepts very clearly bro.

[@KarthikVippala]

Thank you brother 👊

[@ThePortalfactory]

Really thanks. Your explanation was so helpful.

[@KarthikVippala]

Namaste 🙏 capital , thanks for the support, good luck and great health 👍😊

[@bhavanas7914]

thank you so muchhhhhhh 🙏🙏🙏

[@danny_racho]

Hey, you used one input more than needed for P1' at 2:46 You can simplify it from (P1' = ~P1 & P0) to (P1' = P0). But great video and very well structured. Thanks :)

[@prabhakarreddy9729]

Hi Karthik ,as per my knowledge one hot coding also recommend in asic because for debugging it is very easy while when we get timing violation

[@KarthikVippala]

Yes prabhakar , we also use one hot in asic but it suits better for FPGA. Good luck, good health 👍

[@ranjanparnami]

Thankyou

[@KarthikVippala]

Your welcome , thanks for watching so many videos 🙏

[@niharikaj6320]

yes why is eco consideration needed

[@yutinggan1679]

could you pls explain a bit more about the timing path. There are thousands of questions about set up/hold on time violation.

[@KarthikVippala]

Hey Yuting Gan , please check my videos on setup time and hold time video , In future I willl make them Thanks for asking , good luck, good health 👍

[@yutinggan1679]

The way you lecture and the voice you speak are really like my professor at Southampton University. Maybe they can offer you a job there :D

[@KarthikVippala]

😄 , thanks for the other kind words , Can you be specific about the topic so that I can make a video for you 👍

[@yutinggan1679]

@@KarthikVippala I am really flattered to be treated like this. Just do the video as you want, thank you！

[@KarthikVippala]

@@yutinggan1679 your welcome 👍

[@omganeshchoas9097]

Put video on fsm overlap and non overlap detaily with cirucuits connection bro

[@KarthikVippala]

Ganesh , do you mean for sequence detectors or any FSM

[@omganeshchoas9097]

@@KarthikVippala Both bro I am not have that much idea bro on both

[@KarthikVippala]

@@omganeshchoas9097 ok I will make one 👍

[@RailfanArpit]

Sir I have mailed you. Please check

[@VarunsSharma1901]

How to do one hot encoding in verilog?

[@KarthikVippala]

Namaste 🙏 varun , instead of using 0,1,2.. for states we can replace them with 1,2,4,8... In one hot. Thanks for asking, good luck and great health 👍😊

[@lakshyabhardwaj9541]

What is ECO?

[@KarthikVippala]

Namaskaram 🙏 Lakshya, Engineering change order , ECO is the process of inserting a logic change directly into the netlist after it has already been processed by an automatic tool. Before the chip masks are made, ECOs are usually done to save time, by avoiding the need for full ASIC logic synthesis, technology mapping, place ,route, extraction and timing verification. EDA tools are often built with incremental modes of operation to facilitate this type of ECO. Good luck & great health 👍😊

[@uday5786]

what is eco?

[@KarthikVippala]

Engineering change order , ECO is the process of inserting a logic change directly into the netlist after it has already been processed by an automatic tool. Before the chip masks are made, ECOs are usually done to save time, by avoiding the need for full ASIC logic synthesis, technology mapping, place ,route, extraction and timing verification. EDA tools are often built with incremental modes of operation to facilitate this type of ECO.

[@uday5786]

hey karthik ...thanks for the video..i request you to make a video on latch up problem in mosfets

[@KarthikVippala]

Ok uday I will do it , but I need some time for it 👍