is your background Palani by any chance??

You explained this in a very good way Can you please make such more videos related to verilog implementation of all these things

Not understanding particular why are u taking input as 1 at s1 and making remains at s1 only, why are you not taking as 0 input at s1 state

Am not understood what written with black sketch who they happened, at u took 0 at ideal, s1 state going to but how s11 state it self happened

9:50 DID HE SAY DON'T FUC..

Perfect

Really Really Nice Video Man........I have seen many videos of FIFO, but this one cleared all my doubts.... Kudos man

I would watch your videos if you didnt have that fake accent......

bandha- indian accent- american lol😆

Hi Karthik! Since we are only interested in finding the number which occurs once, I think using a series of XOR operations alone should suffice. My understanding is that a counter (or any sequential for that matter) won't be needed - this is very similar to a binary to gray conversion, where you shift the bits and keep doing XOR. Also, the problem statement does not put a constraint on the max size of the elements which the array can have, so attention has to be paid here as well.

Is there any software where we can directly write code and execute them without using cmd?

you're gawd 🙏🏼🙏🏼🤲🏼🤲🏼

Vikram Tina Roles top secret good example 😂😂

Thank you so much❤

More videos needed...❤

explained with a very simple way

I have been came across the problem to divide clock frequency by 2/3 can you help to solve it

what is min pulse width violation and min period violation

At 6:45, what is the guarantee that the signal is going to be to be sampled to 1 ? after meta stable state, the signal may even sample to a 0 value right? how can we know the correct value from 2 flop synchronizer?

Sir can we do this using jk and T flip flops whoes input tied to 1

Sir thank you for doing this ! I have one question for the D Flip- Flop, concerning how we draw the D diagram. Is there a pattern to it, or we can decide ourselves how will D look ? And as I understand, each time we try to draw the vawes for the D flip flop, we can have different output IF we draw a different D diagram ? Thank you !

the wave form at 10:34 looks like clk/2...please correct me?

bro sukran to u, u did better than my sonfofabıtchteacher <3

Great video. Thank you!

Bhai kitna cringe accent hai

Thank you very much

how to solve for 8 bit?

You are so perfectly explained all that in 12 minutes .Thanks for your time !!Excellent Work

For big designs, we can use open source linting tool verilator, it will give warnings which the compiler doesn't.

how are we getting axorb in in down multiplxer?

you are tooo good

The bin has different files.There is ntg called test.v 😭😭😭

Hi, hear in the compilation and simulation command what is the meaning of "dsn"?

Y= A.B bar stick dgm vdd down line is it p diff line or n diff line

Bro what are Flip-flops negatively triggered and what are all positively triggered

Hi, Thankyou so much for clear and concise video. Could you please tell, if i have to search the data in linear manner efficiently. What can be the possible approach? Please respond to the question, it would be great help.

Good information

Why we use asynchronous signals...

One Request bro can make ppt and then explain because u have knowledge.In this paper, the camera is not stable, so sometimes I have problems while learning.

Thank you so much! I have been struggled with this problem for about one month. You totally saved my life!!!🥰

Can u draw the timing diagram for passing multiple signals....

Can you please help me with color coding part of the stick diagram. What will be the color coded stick diagram and mask layout for two input cmos nor gate? Thank you so much for making this video, I'd be really grateful if you could help me with this

Very nice

why don't you stop with that accent ? besides that a good video though

Means a lot sir.... Finally i have understood the concept......

Best ❤

your lecture make me to earn 10 extra marks in my semester exam .

It was the digbee that got me

Thanks Karthik!

Hi Karthik, great explanation, quick silly question: why did you use an xor gate in toggle based synchronizer to convert a level to pulse but an and and gate in handshake based pulse synchronizer to do the same? Thank you