Digital Design & Comp Arch - Lecture 6c: Verification & Testing (Spring 2023)

[@paulbird2772]

0:05 Part 3: Circuit Verification 4:46 Part 4: Functional Verification 5:43 Testbench-Based Functional Testing 9:55 Simple Testbench 11:44 Self-Checking Testbench 17:16 Automatic Testbench 22:09 Part 5: Timing Verification 25:42 Meeting Timing Constraints

[@arifnishan5646]

Very clear informations

[@rjScubaSki]

I wonder if something like TLA+ could be used for defining the golden model, verifying it, and generating test patterns via its usual state space exploration. Obviously not possible for every state in realistic circuits