Part01 Introduction (HLS Programming with FPGAs)

  Рет қаралды 20,458

Youngkyu Choi

Youngkyu Choi

Күн бұрын

Пікірлер: 21
@maryammoghtaderi3456
@maryammoghtaderi3456 Ай бұрын
I can't believe I just found such a course on YT and for FREE! Thanks a lot for sharing it, I really appreciate the clarity of your explanations and the details you have covered in this course.
@gloriamazumdar1547
@gloriamazumdar1547 4 ай бұрын
This is perhaps the best Vitis Video I have every seen. Its an undergrad course but very suitable for practicing FPGA engineers like myself. No exaggeration intended. I have shared this video series with my cofounders in 3 different startups. This video series should be converted into a Coursera or Udemy program for those who already exp. with Verilog or Sys-Verilog or VHDL. Along with the free book from Prof. Castner & his UCSD team.
@johnnyBrwn
@johnnyBrwn Жыл бұрын
You're a genius man. You're helping me out a lot in my PhD!
@satamo1996
@satamo1996 2 жыл бұрын
I have Embedded system Engineering course in masters MSC.Thanks for the video.Sincerely.
@abuali5513
@abuali5513 Жыл бұрын
Thank you for the clear and perfect explanation
@gloriamazumdar1547
@gloriamazumdar1547 4 ай бұрын
There are measures proposed for HLS based design by other authors. The theoretical best ones are from Prof. Keshav Parhi at Univ. of Minnesota. First measure is the Iteration bound . Computation time of each loop divided by the delays in each loop. Maximize this ratio over all K loops. This measure is due to Parhi. Parhi provides a Matrix method to compute the iteration bound.
@fireinthehole2272
@fireinthehole2272 2 ай бұрын
AWESOME VIDEO
@kailuo292
@kailuo292 3 жыл бұрын
Thanks for your upload
@gordonwong892
@gordonwong892 2 жыл бұрын
Thank you for the upload
@iridium3
@iridium3 2 ай бұрын
안녕하세요 교수님 혹시 한국어 강의도 있을까요?
@mehtubbhai9709
@mehtubbhai9709 7 ай бұрын
Does all of the 1000s of lines of Verilog code @5.30 in the video need to be generated by hand or is a lot of it boilerplate code that can be automatically generated? Thanks for the great video 👍
@willcowan7678
@willcowan7678 Жыл бұрын
How come verilog is censored in the video? Proprietary?
@youngkyuchoi4260
@youngkyuchoi4260 Жыл бұрын
No, I was just making a point that a Verilog design is less readable than an HLS design :)
@Bwajster
@Bwajster 2 жыл бұрын
Does Vitis HLS v2022.1 support built-in HLS Functions such as hls::Threshold, hls::Erode, hls::Dilate, hls::Mul, hls::Duplicate, hls::MinMaxLoc, hls::CvtColor etc. ?
@youngkyuchoi4260
@youngkyuchoi4260 Жыл бұрын
I am not too sure, but Vitis Vision Library seems to be supported on Vitis 22.2.
@saadqayyum2148
@saadqayyum2148 2 жыл бұрын
Could you share lecture slides?
@youngkyuchoi4260
@youngkyuchoi4260 2 жыл бұрын
Sorry for the late reply - uploaded to my website at sites.google.com/view/ykchoi/teaching
@saadqayyum2148
@saadqayyum2148 2 жыл бұрын
@@youngkyuchoi4260 Thanks
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