Processor Architecture : Data Bus Address Bus and Control Bus | ECT206 | CAM | KTU

[@rosmithomas7823]

Thank you sir....

[@asifshahkutty4474]

Basically control signalsum bidirectional alle. (8085 processorinte casel RD ', WR' pole ula signals output signals aanenkilum READY signal input signal alle..) 13.24 timele figuril clear aayi koduthittund.. CPU and control bus thammilulla connection bidirectional aanennu.

[@ShastraTechnicalInstitute]

Some control signals are unidirectional very few of them are bidirectional !

[@asifshahkutty4474]

@@ShastraTechnicalInstitute Yeah agrees to that. But oru general block diagram aakumbo unidirection kanikkunnath misleading aakille ennorru doubt. Thats all. Anyway nice presentation ..

[@abhishekrmenon8664]

Thanku very much sir

[@huraiceshajahan3639]

Sir module 1 inte baaki potions inte video cheyyamo

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Sir ee notes ellam.share cheyyaamoo

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Thankyou sir

[@beenaraghu3012]

Sir important topic parayo

[@ambikaunni1704]

1 KB yum 1K yum same ano

[@ShastraTechnicalInstitute]

Yes

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@@ShastraTechnicalInstitute Thankyou sir

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Plz upload COA for CS

[@NeighborhoodAI]

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[@anamikaajayan8887]

Notes kitaan vazhi indoo🥲

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Note pdf undo sir

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[@amrithakr2992]

Sir notes shariyamo?