Python and SystemC: A Dream Team for Building and Analyzing Virtual Platforms

Presented at DVCon Europe 2021
Session T2.2
Today’s electronics devices are dominated by ‘system on chips’ (SoCs). A complex system like a SoC involve many development teams with various focus areas. Examples are HW architects, HW verification teams, FW developers, SW verification teams to name just a few. Each of those teams often require a slightly different view of the full system. A ‘one thing fits all’ approach is very unlikely to find, at least before the HW is available. This situation drives a variety of techniques during development e.g., virtualized models, Virtual Platform models, FPGA accelerators, HW emulation, HW simulation.
The various use cases quite often require a certain amount of flexibility. For instance, to evaluate architectural variants, support product variants or partitioning of complex systems in order to keep simulation speed reasonable. Also augmenting the simulation with stimulus and analysis capabilities to gather information out of the generated data is commonly required. In practice scripting is being used to integrate all the various elements and steps addressing the VP user’s needs.
This tutorial aims to give an overview of the development and deployment of VPs as well as results analysis using Python as scripting language. Use cases are not only in the semiconductor vendor domain but also at its customers. The use cases will be illustrated using (live) demos of the various approaches and the combined use of the elements. The tutorial will also show how Python can be efficiently used while maintaining the performance by connecting to high performance models written in C++.
The first part focuses on building and running VPs and variants based on Accellera official PySysC. It will highlight motivation and background to the development of the Python module. Here the use of PySysC will be demonstarted to get to a kind of ‘VP Construction Box’ approach allowing easy and flexible virtual platforms composition. It will also show advanced uses of the methodology to partition VPs for simulation speed improvement or quickly building user interfaces to ease working with the platform simulation e.g. for embedded software development.
Presenter:
Eyck Jentzsch, MINRES Technologies GmbH
Thomas Haber, Toem GmbH
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