BJT push-pull gate drivers: when good intentions lead to a bad design

[@hamiltonqrn2734]

The most solid channel about electronics on youtube. You're becoming immortal, prof. Sam. Thanks for sharing such great knowledge!

[@sambenyaakov]

Wow, thanks! Comments like yours keep me going.

[@2meters2]

I started using driver (chips) with Mosfets with split outputs, as shown in 9:44 on the left, and then using a separate resistor for on and off switching. It solves all the issues outlined, saves a diode, and I never looked back after that.

[@sambenyaakov]

Thanks for sharing. Yes, this is probabely the best approach

[@miklov]

Funny timing, I just recently looked into discrete gate drivers (because I did not want to have to wait on components). Never thought of the Miller model nor realized there could be Miller spikes. Thank you for an interesting and enlightening presentation!

[@sambenyaakov]

👍🙏

[@dimanovo]

Hi Sam, thank you for this important and clear explaination!

[@sambenyaakov]

Thanks Dima😊

[@SmithKerona]

As an ancillary information to what you have presented professor, I remember reading on one of the IEEE semiconductor journals that breaking down the BE junction (of course with current limiting) of a BJT degrades the hFE. The BE junction is a lot more sensitive compared to the BC junction which can be broken down without any ill effects on the transistor parameters. Therefore, every time the gate drive is going high (which you have demonstrated that it breaks the BE junction) the hFE of the PNP device is getting reduced thereby reducing its effectiveness as a buffer.

[@sambenyaakov]

Thanks for sharing this important information.

[@tefatronix]

I can confirm this - did some experimentation with a few jellybean BJTs. Even a few mA over some tens of seconds to minutes decreased hFE significantly. Even less current has a significant effect given enough time, the damage seems cumulative. By torturing the transistors a bit more, hFE decreased by tens of % easily. Interestingly passing enough current through (in normal active mode or through the junctions in forward mode) the transistor to heat it to about 200+°C for a few seconds almost fully reversed the hFE loss. If I recall correctly, even heating it externally with no current had a similar "repair" effect. Sorry for potentially imprecise info and non exact numbers, I did this a long time ago. Maybe I'll redo it in a more controlled manner ... There is an article with the name containing "degradation of BJT parameters..." by Toufik with more info, interesting read. In a few datasheets of precision BJT based devices (super match pairs? Op-amps? Sorry, not sure) recall seeing protection diodes on the BE junctions...

[@sambenyaakov]

@@tefatronix Thank you for further sharing the very important information which I was not aware of.

[@sambenyaakov]

@@tefatronix May I post your comment with credit to you at my LinkedIn channel www.linkedin.com/groups/13606756 ?

[@tefatronix]

​@@sambenyaakov ​Wow, thank you very much :) no problem with that, but please keep in mind that I can't 100% guarantee it's absolutely exact, as I did the experiment a long time ago. Anyway I found the article by Toufik et al - the experiments correspond to it fairly well. The title is "Degradation of Junction Parameters of an Electrically Stressed NPN Bipolar Transistor", it's on Hindawi, but YT deleted the previous comment with a link.

[@mohammadhassanzade6893]

great video thank you mr professor

[@sambenyaakov]

👍🙏🙂

[@GHOTIME]

Thank you Professor

[@sambenyaakov]

Thanks

[@Paxmax]

13:17 When EE's fall asleep at the wheel ¯\_(ツ)_/¯ My own funniest / simplest / dumbest brain fart was not reading the entire datasheet when selecting a rail-rail Op-amp. It was used basically as a multi-channel DC peak detector. There was this confused bewilderment why I never got more than 2.5V out inspite having 15V in. The chosen op-amp did not allow more than 2.5V differential between the signal + input and signal - input! There was some internal diode structure inside op-amp between inputs, just shunting any excess. Ooopsie. Now the double moron whammy was that the chosen op-amp did not really have a standard shared pinout So, awaiting the next iteration an "off-the-shelf" generic op-amps in lab had to be criss-cross wire adapted to limp forward. -Note to self: Yes! you must read the entire datasheet even if it feels like you've read 15 identical before, have a litlle think, then push the "buy" PCB button ...or live with limping prototypes. That was decades ago, I'll never forget this lesson. though

[@sambenyaakov]

Indeed. Thank for sharing or thoughts

[@moriergael2023]

very interesting as usual thanks 😊

[@sambenyaakov]

🙏😊

[@RexxSchneider]

The biggest problem with driving the MOSFET from the collectors of BJTs is that the BJTs in the simple circuit go into saturation and that results in a delay when the transistor transitions to the off state. The end result is an inability to drive the MOSFET at high frequencies. You might consider using a clamping Schottky diode from base to collector preventing saturation as is done in the 74S/LS families of logic gates.

[@bskull3232]

Adding an SBD will totally shunt off any current from the BE junction, rendering a common-emitter amplifier design completely useless. You need to balance shunt current ratio so that during a transient, the majority of current flows through BE junctions, and during DC state, current flows through SBDs, and this might be possible to do with a ballast resistor for the SBDs. Though, I've not simulated or measured such a circuit, just something popped off my head.

[@RexxSchneider]

@@bskull3232 I think you've misunderstood how the SBD between the base and collector works. The diode is connected so that it becomes forward biased when the collector voltage falls below the voltage at the base and clamps the collector to no more than about 300mV below the base, i.e. the collector voltage will drop any less than 700mV-300mV = 400mV above the emitter and therefore does not enter saturation. The diode effectively shunts excess base current through the collector and keeps the transistor just on the edge of its linear region. Without the excess of charge carriers that is typical of saturation, the transistor can recover quickly and speed is much improved. If you still don't understand, I recommend looking at an article on the "Schottky transistor" on Wikipedia or elsewhere.

[@sambenyaakov]

Hi Rex, a discrete buffer that drives the MOSFET's gate from the collectors may not be practical since it requires a complex circuitry to drive the BJT's

[@triffid0hunter]

Ooh my comment got quoted in a video!

[@sambenyaakov]

👍🙂

[@davidblank1360]

Hello Professor Ben-Yaakov, In the Micrel driver, at 10:10, the Gates and the Sources of the driver FETs are shorted, so when one FET is just beginning to turn ON with Vgs=Vth, the other one is already commanded OFF by the opposite polarity Vgs. Due to the fact that FETs are a majority carrier devices, which do not need a minority carrier recombination process, the duration of a possible shoot-through situation is very brief, governed by the internal small Rgg of the FETs. All this is trivial, of course. The thing is, it looks to me, that in this situation, the slower the transition is, the less shoot-through there will be, not the other way around...

[@sambenyaakov]

Not so. at 1/2 Vcc both are conducting.

[@davidblank1360]

@@sambenyaakov You're right, of course! The Drains are shorted, not the Sources...🤦🏻‍♂🤦🏻‍♂🤦🏻‍♂🤦🏻‍♂ Thanks a lot!

[@rcinfla9017]

There are some commercial MOSFET driver I.C.s that provide separate pull up, pull down pins for gate drive.

[@sambenyaakov]

Indeed. But the point of this video is that this particular configuration is unsafe due to possible breakdown.

[@wojciechbajon]

There is an error in the explanation 8:00. The voltage of two diodes will never remain there. Yes, it will be like that at first. The junction will be discharged to 2xVD (1.5v) at a rate limited by R2(*). But this is not the end of the discharge, because the discharge continues through R1 (at the charging speed). (*) More precisely, with the equivalent resistance resulting from the parallel connection of R1 and R2. (With the additional difficulty of the junction resistance of the additional diode.)

[@sambenyaakov]

Thanks fr commnet but I think everything is OK. 1. The discussion is related to "Miller spike" so what matters is when there IS a current not what happens later. 2. If one wants to be more precise then the current limiting effect of RB plus the output resistance of the primary driver need to be taken into account.

[@paradiselost9946]

i came across a brief mention on some site about having them the other way round... pnp over npn, much like the fet versions with pchannel over nchannel. (searched and searched, and im not finding it again... its not anything on stackexchange, etc...) having absolutely no further information... took a while to figure it, it likes releasing brown smoke. but after some headscratching, it definitely is the better way to switch. virtually no impedance to either rail when appropriate BJT is conducting. its just hard to set up as a switch. the input has to swing PAST the rails, and has to be driven HARD. no linear region, as square as possible... or the tied bases just draw full current and smoke appears. that gets into...whats its name? shoot through? was definitely the first time ive actually been able to see the effects of using a lower than specified gate resistor, 2R7 say rather than 4R7... excessive ringing. to the point of destruction. and taking that 4R7 to say, 10R, even better at 47R..., soon demonstrated why they often use 2W resistors... they smoke. and ironically, the larger the resistance, the faster they smoke. that... wasnt expected but makes sense. and of course, the switching of the fets slows down. can read all the books, do all the math. nothing teaches like doing it practically.

[@sambenyaakov]

Don't you have a sever shoot through problem with pnp and npn?

[@sambenyaakov]

@@paradiselost9946 2n2222/2907 nota good choice for date drive

[@huanzhou4768]

Hi Sam thanks for your video. I have just one question; when usig push pull (transistor bipolaire) )to drive the Mosfet / IGBT, the peak current in fact is not like (Vcc - 0.6V) / Rgon or (Vcc - 0.6V) / Rgoff, during the simulation, the Vbe is not really 0.6V, it is varie between 4 et 6 V , so the peak current is not really high. My question, why the Vbe value is changing, it is not 0.6V during the very short charging / discharging time of Mosfet ? Thanks

[@sambenyaakov]

"My question, why the Vbe value is changing, it is not 0.6V during the very short charging" you mean Vbe or Vce?

[@huanzhou4768]

@@sambenyaakov yes , I mean the Vbe is not 0.6V, and Vce is also high; the Vce is not neglected

[@tamaseduard5145]

🙏🙏🙏

[@sambenyaakov]

😊🙏

[@NiHaoMike64]

What if the current limiting resistors were put in series with the collectors instead of the emitters?

[@sambenyaakov]

Putting a resistor at the HS is done in practice. For the low side it is not a good idea. Give it a try. If you give up write again. Hint: why is it good that in the conventional driver the BJTs do not saturate?

[@danstiurca7963]

Great video. The only problem I would ask is... why would anyone even consider using BJTs for anything having to do with switching. BJTs are for analog, FETs are for switching. Easy. :)

[@sambenyaakov]

Still, BJTs are used as buffers for gate drivers😊

[@danstiurca7963]

@@sambenyaakov not by me. 🙃

[@sambenyaakov]

@@danstiurca7963 Are you using MOSFET gate drive buffers? In what configuration.

[@danstiurca7963]

@@sambenyaakov I haven't used a gate driver since power electronics lab in college. That's what switching controllers are for. :) ... but I did use your npn gate pulldown trick to save half a watt on an LT switcher, and that was a nice surprise! You'd think it would have been optimized already...

[@sambenyaakov]

@@danstiurca7963 👍

[@smeggyhead1]

3:06 could that be solved by adding a capacitor (ensuring the time constant with R1 or R2 isn't too small) across the 2 emitters?

[@sambenyaakov]

I think this will mess up the gate drive signal. Try to simulate. I will love to see the results.

[@smeggyhead1]

@@sambenyaakov Hi Sam. I don't think that would make any significant difference to the drive signal. However, I have just realised the addition of that capacitor would essentially put R1 in parallel with R2, so not really a good idea anyway.

[@sambenyaakov]

@@smeggyhead1 👍

[@anonymous_IIT]

@1:33 NPN will start to conduct as soon as its 𝑉𝐵𝐸 is roughly 0.7V, but how will that happen when its emitter terminal is floating? May I assume MOSFET and it's gate capacitance is discharged at the beginning which provides 0V to the node connecting the emitters of NPN and PNP ? I guess my question is in large part about the circuit's initial conditions and my assumptions about them, but feel free to set me straight.

[@sambenyaakov]

Current is flowing during the charge and discharge of the MOSFET's input capacitance.

[@anonymous_IIT]

@@sambenyaakov in that case driver would not work without capacitive load?

[@HL65536]

So the reason I was fine using it is that my drive voltage was 5V. Will use Mosfets for future Arduino gate drivers.

[@sambenyaakov]

With 5V everything should be OK. Nut in many applications %V keeps the Rds somewhat high. If you use 15 volts and you don't see breakdown. I would not recommend it. One should never exceeded the Absolute Maximum Ratings.

[@etmax1]

I often use paralleled HC or AC CMOS buffers for Arduino applications because the square wave input is well separated from the output and the transitions are fast enough that cross conduction currents are negligible at typical switching speeds. Now if you start driving GaNs instead of snail pace IGBTs or regular MOSFETs it's a whole new ballgame.

[@Spark-Hole]

At 1.12, can anybody explain why would someone like turn on to be slower than turn off.

[@sambenyaakov]

See kzbin.info/www/bejne/aKC8ioyMqpl0oc0

[@nyyotam4057]

A question about the circuit given at 13:07, which I'm sure you know someone will ask, so let me be the one who asks it: Regardless of the fact this will immediately short the power supply, obviously - there are two BJTs in the flipped push-pull, both the top and the bottom ones are given in a CE configurations here. A CE configuration inverts, so why wouldn't the flipped version invert?

[@sambenyaakov]

Not sure I follow you

[@nyyotam4057]

@@sambenyaakov Well, the question is, basically, why wouldn't the circuit given at 13:07 invert (give low voltage to high in the input and high to low in the input)? Or maybe it doesn't matter cause you say "so what if it inverts, just feed the signal to the gate of a P-channel"?

[@edinfific2576]

​@@nyyotam4057 The problem is that for either BJT to be off, its BE voltage needs to be below 0.6V, so the signal driving them will have to go from

[@nyyotam4057]

@@edinfific2576 Sure. My point was that besides the clear problem (obviously, shorting the source), this entire construct of the flipped push-pull will not actually be a push-pull but a not gate. I absolutely agree with you. That the input voltage has to be either below 0.6V or above Vcc-0.6V otherwise both BJT's are on and the source is shorted. Wasn't arguing with it.

[@dr.dharmrajghodke974]

Sir, if instead of ground to +ve supply gate drive, biased with -5 V, to + V, still this this phenomenon repeats?.

[@sambenyaakov]

5 volt should be OK. But at 5V drive most MOSFETs do not reach the lowest Rds(on)

[@dr.dharmrajghodke974]

@@sambenyaakov -5 negative drive instead of ground. Still this problem persists?

[@abhijithvp199]

I guess if we add a series zener of ~3V with capacitor in parallel and increase Gate drive voltage to 18V to compensate this for turn on, the miller spikes at gate should increase to -3+2*Vd ~ -1.5V+R_drop maximum at Gate terminal.

[@sambenyaakov]

@@abhijithvp199 I am for solid and robust engineering design

[@nyyotam4057]

Coming to think about it, how about two CE in series as a gate driver? Yeah, I know its a silly idea.. But still, why not? EDIT: I can answer this myself after running the transient simulation: Because you have then a double reaction time ( the reaction time is not a direct result of having two BJT in series but rather of the fact that an inverter takes time to rise its voltage or drop it - and here we actually have two inverters in series ), which defeats the whole idea of a driver. But still, I guess there are certain special circumstances when you can use this as well (when you don't have a driver IC and speed is not critical, for instance). Well, in fact, a couple of weeks ago I happened to need to use a DDS output as an input for a current-consuming device. So I did a simple push pull and it worked flawlessly.. So you don't really need anything else. Especially not two CE in series which will cost in reaction time. However, if you only have 0V-5V and the signal is also 0V-5V then I guess maybe the two CE in series could still be a viable option sometimes, since the top EB diode in the push-pull "costs" 0.7V, so maybe then.

[@sambenyaakov]

Indeed. Thanks for sharing your thoughts.

[@carloslemos6919]

Why it is desirable to have turn on slower than turn off?

[@sambenyaakov]

See kzbin.info/www/bejne/pZfCp2WEastqbpo

[@Pops180]

Why would you ever use BJTs to drive a FET? Seems like a waste of the benefits that a FET would offer.

[@sambenyaakov]

For the case of a single gate driver that needs to drive a number of MOSFETS in parallel, the BJT push pull buffer is an excellent solution. You know of a better one?

[@Pops180]

@@sambenyaakov push pull isn’t the issue. I think MOSFET push pull drivers as in the datasheet you reference is the better solution especially if you are worried about the current capability of the source.

[@sambenyaakov]

@@Pops180 Sure, but in the real world we worry about the cost and BJTs are more economical and work wonderfully.