SeqCkt - 3 - Master Slave Flip Flop

[@gayatri5397]

1. Why are we using the inverters at the circuit implementation of the transmission gates? 2. We are using 2 inverters so that the given inout does not change at the output right?

[@APARN-x9b]

1. to characterize the flip flop 2. yes

[@satirthapaulshyam7769]

T setup flop=t setup L1 Cz L1 is a -ve lvl triggered and being a -ve lev trig it has a sampling edge of +ve edge so its setup time should be the setup time of flop cz if u think it as a flop(+ve edge triged) the flops setup time is D's D1 to pos edge of clk and the L1 being a -ve lvl triged its setup time is also the same but L2 s setup ttime is D's D2 to -ve edge of clk