SPI Master with Chip-Select in FPGA, VHDL Code

Here we add in Chip-Select to the existing SPI Master to allow for talking to interfaces that require a Chip Select (CS) or Slave Select (SS). These mean the same thing. This is in VHDL.
Support this channel! Buy a Go Board, the best development board for beginners to FPGA:
www.nandland.com/goboard/intr...
Like my content? Help me make more at Patreon!
/ nandland

[@paulmichael3694]

Fantastic video. Thank you!

[@feiveljethro4275]

Do have a platform for the fpga's fans to discuss?

[@tomurkin5563]

Can you please comment on how to connect multiple drivers to a certain net via tri-state logic? For example in multi-slave SPI system, based on the CS signal only one of the slaves will generate a binary output for the "CIPO" while the rest will generate a high-z. However, when i try to simulate it i get the 'multiple drivers for a net' error - which in this case is intentionally. Thanks!

[@Jm-my1rd]

I use 17.1 Quartus compiler and it's giving me an error as shown below: Error (10481): VHDL Use Clause error at SPI_Master_With_Single_CS.vhd(84): design library "work" does not contain primary unit "SPI_Master". Verify that the primary unit exists in the library and has been successfully compiled.

[@playdo93]

That error indicates that you haven’t first compiled the “SPI_Master.vhd” file into your work library. It needs to be compiled into your work library first since that component is being instantiated in a higher level entity. Hope that helps

[@maggen5]

How do you handle this code if you don't need to receive anything?

[@abdessamadbenjaa1639]

I have problems when i compiling the code