It's really hard to find hardware tutorial, there should be more hardware content in the world.
@MrKaizen753 жыл бұрын
Check out Vipin Kizheppatt's channel
@rahmatdwiputra5 жыл бұрын
Thanks!! the world is in need of more fpga content!!
@vahanabrahamyannАй бұрын
I think its not good idea to use registers like SPI clock.
@fmm5322 Жыл бұрын
I want to ask another question. How to read the contents of the register in verilog through spi. We knoww the addrsss of the first register. Then the address auto inreements
@sumitpahuja28584 жыл бұрын
I am unable to simulate this code xilinx ise 14.7. please suggest me another one
@recurentgamer11424 жыл бұрын
Thanks for the tutorial, but I think it would be nice to put an IP-core visual representation of this SPI, i.e. box with all i/o, etc listed within the code.. Should it be 2 SPI modules? Data comes from a source to TX on Master, then Master transfers it via MOSI to Slave?
@ngocmanprocoder6 ай бұрын
Hi, i have a question, and i need your assistance. In a system, we make transfer with single port sram through spi protocol instead of transfering directly. Why? Many thánks
@RenegadeFury3 жыл бұрын
Thanks for making this video, at 5:55, why does there need to be an extra delay for the output spi clock? Is it because you are using one cycle to copy the data on the input? also does the half bits per clock really need to be 2 or more? It seems like it would work with a value of 1 from looking at this EDIT: I see the need for delay for the output spi clk, it's because you are basing the output of the spi_clk on r_leadingedge which is already a cycle behind
@fmm5322 Жыл бұрын
Please answer my question. U seem the most relevant
@fmm5322 Жыл бұрын
Whats the purpose of " r_SPI_Clk_Edges" in the context of spi mode and no of bits to transfer in that SPI transaction
@jcudia94855 ай бұрын
watch the video🤣
@ayyappana9101 Жыл бұрын
Hi ! Can you suggest how to interface spi flash with spartan 6 to write and read user data
@naveenbodige46855 жыл бұрын
can you send the simple verilog code for SPI
@ravindrabisram1375 жыл бұрын
In case you haven't gotten it yet, its on GitHub. github.com/nandland/spi-master/blob/master/
@MrRamsampath3 жыл бұрын
Can you please share the specs which you referred for developing code?
@smilingthogth7792 жыл бұрын
Hello sir, how can get this verilog code?
@fmm5322 Жыл бұрын
Two very basic questions 1. In MISO always block why you need to check the (o_tx_ready) signal.??? 🤔. o_tx_ready is the flag generated by the spi master to tell the upper module that its ready for next transmission on MOSI.. 2. In first always block where we are counting the edges of the master clock (i_clk) to generate the spi clock edges.. Kindly elaborate who the trailing and leading edges are correlated with this count?
@fmm5322 Жыл бұрын
Anyone please
@egegoksu95576 ай бұрын
Hey, have you found an answer for 1st question?
@fmm53226 ай бұрын
Nope.
@StrsAmbrg3 жыл бұрын
What is the programming language you are using? Look like Pascal, but is not.
@junpenglu66275 жыл бұрын
Thanks for the video! I have a question on how we should utilize or modify this code if we need to transmit and receive data 2 bytes at a time instead of 1 byte at a time as shown in the code?
@ravindrabisram1375 жыл бұрын
I also have this question
@fmm5322 Жыл бұрын
Make clock edges from 16 to 32 with counters updated from 3 bit to 4 bit
@Ravikumar-kb8fn5 жыл бұрын
How to convert SPI to I2C protocols using Verilog Code??
@geoshah3 жыл бұрын
What's the function of the code reg [2:0] SCKr; always @(posedge clk) SCKr
@Nandland3 жыл бұрын
Creates a shift-register.
@fmm5322 Жыл бұрын
@@Nandland answer my questions please
@hanbyeolkwon5595 жыл бұрын
Thanks for really helpful video. But I have a question that how to make and send 'real' signal in FPGA. I mean, if I want to SS low at specific time how to do it?? not for testbench.
@Nandland5 жыл бұрын
The only source of truth is your clock. Time does not exist to an FPGA. Only clock pulses. So you need to 1. Know the clock frequency. 2. Count clock pulses. That's how you know anything at all about time.
@hanbyeolkwon5595 жыл бұрын
Maybe what I have to do is make counter and signal in the top module. It would be harder than I thought.... but thank you for your answer!
@qigao54585 жыл бұрын
I feel so hard, what ability do I need to understand?
@mo9383 жыл бұрын
Practice. Never give up.
@ajtechnologies41854 жыл бұрын
$CLOG2 is giving error in synth
@Nandland4 жыл бұрын
What's the error? I suggest posting your full question and the error to stackoverflow.com.
@ajtechnologies41854 жыл бұрын
@@Nandland ERROR:HDLCompilers:26 - "Code.v" line 60 unexpected token: '$clog2' ERROR:HDLCompilers:26 - "Code.v" line 60 expecting ':', found ')' that is line 60 of your github code.
@unfrostedpoptart4 жыл бұрын
@@ajtechnologies4185 $clog2 has been around since Verilog2005 and in SystemVerilog. What synthesis tool are you using? How old is it?
@marrytran77033 жыл бұрын
@@unfrostedpoptart Hi David, I also have the same error like this when using Xilinx Tool: ISE-Design Suite 14.7. I haven't fixed it yet, Could you help me suggest the solution for that error? Thank you so much.
@mrrtommyversace36185 жыл бұрын
Hello. Greate video, thx for your work!
@monfry2675 Жыл бұрын
God bless you !
@SiavashRaveh5 жыл бұрын
Hi, you have sold this tutorial on udemy
@Basti1987chiller Жыл бұрын
can we please all come to the conclusion that the programming language we use is C