SRAM PART 4: Read, Write & Hold stability criteria and margin (SNM) of an SRAM (PART-2) (2023)

Topic: SRAM Read, Write & Hold margin and criteria (PART-2)
Viewers: Who has a VLSI course or SRAM related project & research work.
Briefly discussed data stability during read & write operation of an SRAM memory cell. During read or write operation the data can be flipped or lost. Also for a long duration, stored data can be lost. Described the reasons behind the above situations and also the solution to these problems.
About this video series :
In this series, we will briefly talk about the core principle ideas of the SRAM cell and then design a 2x8 16-bit memory unit using the SRAM cell with read, write, and output circuitry in CADENCE VIRTUOSO.
If you have any confusion please let us know in the comment section. Thanks for watching it.

[@andrewfield6364]

You said at the end you were going to make a SRAM in Cadence Virtuoso? Need to see this video! You have great explanations, so helpful!

[@descreteinfo5663]

Very nice explanation sir. Hidden 💎!

[@ngochuy7683]

thank youu!!

[@janicesweedal4877]

Can you please make a video on SNM

[@hbtech501]

Sir when would we get SRAM Part 5? Eargly waiting for it.