Successive Approximation ADC Explained

[@omi5137]

Thank you very much for these clear videos. You are helping tons of future engineers here!

[@language_loom]

You guys are helping me from my 1st sem and now even during this crisis... Tomorrow I got exams (online) but this made it so easy thanks 🙏🙏🙏

[@language_loom]

@Felipe de Souza I didn't study ADC in 1st sem.. I had basic electronics in my 1st sem

[@hrishekesh7609]

Online dhana vro, maja va copy adika vendiya dhana

[@jrohit1110]

BRO, you teach better than my profs. Way better

[@shrutimukherjee8378]

My profs don't even teach!!

[@dineshchandra7844]

@@shrutimukherjee8378 🤣🤣🤣

[@kaustavkumarkhanikar753]

Tomorrow is my exam and the irony is that everything taught here is exactly same as my teacher's notes.(every word)..

[@Hariprasad-cq6ud]

He might have copied lol

[@ALLABOUTELECTRONICS]

The timestamps for the different topics covered in the video: 0:34 Working of SAR ADC 6:40 Typical Specifications of SAR ADC 7:33 Advantages of SAR ADC

[@vijayakumarr3519]

Sir how may videos are left to complete DAC and ADC ?

[@mikmik3965]

Youre on e of the best electronics channels there is

[@bhuvnendrapratapsingh7560]

loved that you provided notes in the description

[@leeleslie4167]

so good, one times watch and makes me understand,you are really my sarADC GOD

[@petemitchell9996]

Man u are the best. This video is so well explained.

[@SebastianRamirez-jr6bs]

SAR ADC explained so easily and with such detail!

[@makingwaves-j7]

Bro u teach better than my lecturer 👍

[@utkarshkothimbire1484]

Thank a lot for explaning in simple language.

[@geethakatke1357]

Thanks sir, your videos is very good in Explanation and your voice is clearly listen, so without any difficulty is it easy to understand your videos.

[@akhiladh3247]

Thank you so much for this video. It helped me for my seminar

[@KamalJ5]

Beautiful and easy to understand explanation... Thanks

[@yashavanthakumar3968]

Taking example is beautiful sir thats y it is better then other vedios . Required to change the just below the title of the words it is make better and thank u sir

[@edgarzoe2715]

Thank you for this video bro, really helped me a lot

[@denebvegaaltair1146]

I'm not dumb I just never had you as my teacher.

[@madhubellam651]

Really great bro helped for my sem Exams

[@sagarjaiswar5597]

Great Job!🙂

[@pgtwolf9542]

My prof said me to watch your video

[@gr8vijay]

Excellent video. Perfect explanation. Thanks a lot.

[@Pranav.Suryawanshi07]

Today is my exam and I watched it now how talented am I !!!

[@AnandKumar-oh7zv]

Nicely explained

[@spencercurry8982]

Nice video mate!

[@Truth-qe6sf]

nice explanation. Can you also provide explanation in detail control logic and capacitive DAC for this SAR ADC.

[@salishussain1184]

tommorow is my exam thanks so much

[@C-Cneha]

Awesome explanation sir😍

[@salishussain1184]

simply perfect

[@bhumikamathil5246]

Wow...sir very good explanation

[@rajavikrampullem7583]

Superb explanation..

[@user-fz1nx3wc4s]

Very informative. Nicely done sir.

[@mayurshah9131]

Just Superb 👌👌

[@rahulsutar9042]

Like, share and subscribe .

[@danishnaseer9808]

amazing job

[@johnwang2856]

Clear explanation! Help me a lot!

[@iamklevy]

thank you that was very informative & helpful bro

[@nachobalasch]

Super Useful! Thank you

[@chintanpatel2507]

Best explanation 👌

[@saikiransivaji3378]

Tomorrow is gate exam...iam learning today...thank u sir😁😁

[@ALLABOUTELECTRONICS]

Good luck.

[@detectivekwon5867]

Thank you for this video!!!

[@geshbenrewand1778]

God bless you

[@adityaraja8276]

beautifully explained

[@rinukabhadreskumar1196]

Clear explanation.. great

[@NIKHILKUMAR-xr7ii]

Nice explanation !

[@arunsai3426]

Good work bro clearly understood 😊

[@PeetHobby]

Great video! Successive Approximation ADC seems to be one of the slowest ADCs, right?

[@theonkarsathe]

Great 👌😊

[@Frejjan]

Great video, thanks!

[@sayanbanerjee2722]

Very good explanation sir

[@dhirajkumarsahu999]

Sir, I got a doubt at 6:57 , you said the conversion time is independent of the input, but consider the case when the input is 8 volts and the reference is 16 volts..then it will take only one clock pulse to complete the conversion, hence its conversion time will be very less.

[@Denbo68]

Actually not. The comparator doesn't test for equality, it just tests if Vin is greater or less than the input from the DAC. There isn't a way for it to know it was correct until you go through each successive step until end of conversion.

[@KishanIndiaDev]

@@Denbo68 Sir Please show us how to solve for 8v input

[@chotabheem6937]

@@KishanIndiaDev If u dont get how that Vdac becomes 8,12,10,11... Fill value of a1,a2, a3, , a4 in the Vdac formula where Vref= 16V . Solve it and u will get ur answer

[@luanaaparecidagomes5614]

Great job

[@tavishishaw3782]

thank you so much, u helped me a lot

[@Snpati16829]

Nice explanation 👌 Help me lot

[@matiasacevedo2383]

If you have a 12-bit SAR converter operating at 1MHz, what will be the maximum sampling frequency to use in hertz?

[@ALLABOUTELECTRONICS]

see the conversion time for this ADC is at least Nx T clk = 12 / 1 MHz = 12 us. That means you can not take the sample before 12 us. So, max. sampling frequency, is 1/12 us = 83.33 kHz. So, this is max sampling frequency in ideal case. Considering the settling time of sample and hold, the overall conversion time would be slightly more than that. In this case, may be around 15 us. So, with that, if you calculate, then the max. sampling frequency would be around 66 kHz. I hope, it will clear your doubt.

[@alyalsayed6637]

thank u for this awesome video

[@lowchenkhang680]

Hi, how do u get the 2,4,8, 16? And what if the reference voltage is 12V with 8 output lines?

[@aishwariyamoorthy1062]

Thank you so much!!!!! :D

[@nadeemasif2406]

Question: Let the analogue value of an input signal is 5, for reference value 1 for ADC. Considering that the ADC is 4 bits, write down at least 6 iterations to show the ADC process using successive approximation method (showing update in the binary digits of 4 bit). Please solve

[@rofiqulislam4640]

Vin>Vadc then output is high and Vin

[@ALLABOUTELECTRONICS]

For Vin = Vdac, the successive approximation algorithm remains same.( It is same as Vin > Vdac) Hence, you will get the same comparator output when Vin = Vdac. ( Similar to Vin > Vdac)

[@Sourav_Soumyajit]

Nice explanation! 😊

[@vijayakumarr3519]

Please solve 1 or 2 GATE question in between that would be helpful to understand kind questions asked and how to approach those question. Thanks for all these videos.

[@ALLABOUTELECTRONICS]

I used to post the questions in the community tab every alternate day. You will find the questions related to the latest as well as the older videos there. (And solution as well). Do check the community section of the channel.

[@bhavanarao8727]

What if Vin becomes equal to Vdc?

[@onelivingsoul2962]

Resolution upto 20bits? Not possible. The Noise floor itself limits the effective number of bits to around 14bits Enob. There are various issues like C-DAC mismatch, KT/C noise of S&H,Buffer non linearity,DAC settling issues, SNR due to Clock skew &jitter etc. SAR is used in Async mode in recent times and it is not possible to reach beyond 10bits with just SAR alone. That's why Pipeline architecture exists and that's why Delta Sigma exists. Only oversampling ADC provides 20-24 Enob. In this video only basic SAR algorithm is explained. I can write a book based on SAR itself,that's how vast that is.

[@RushilChopra101]

Thanks sir

[@monafarouk2008]

gr8 explanation

[@user-ph4ce4sj5n]

thank you :)

[@shanejohnson9002]

great job

[@krishnakhandelwal9466]

8:21 Latency for successive approximation is zero but value will not be accurate. To get accurate value latency has to be equal to no. cycles of resolution bits. Correct?

[@ALLABOUTELECTRONICS]

Thats the conversation time of the ADC. The conversion time for any ADC is inevitable. But here 0 latency means, after that conversion time, you will get output. Let's call this conversion time as Tc. For any ADC if converted data is available after let's say 2Tc, then we can say that it has two cycle latency. It means the data is available after two conversion cycles. The latency is very common in pipeline ADCs. I hope it will clear your concept about the latency with respect to ADCs.

[@krishnakhandelwal9466]

@@ALLABOUTELECTRONICS Ok. Understood. But I think latency should be defined as number of cycles it takes to give correct output. Meaning if a 10bit adc operating @5v get 3.3v analog voltage, than successive approximation will take 10cycle to generate 675 (integer equivalent of 3.3v). I agree that at 1 cycle itself will get an output. But this output will be far from 675. Correct?

[@arjunmahajan5760]

why have you not divided by 2 again in 2nd iteration? our SAR output is 1100 which means vref=12v and vdc=6v right? in first iteration you have done this thing only?

[@ALLABOUTELECTRONICS]

Here Vin is 11.2 V. After the first iteration, VDAC = 12V. Since VDAC > Vin, so second bit will be set to 0 and next bit will set to 1. That corresponds to 1010 or 10V. The algorithm is, if Vin > VDAC then current bit will be kept as it is and next bit will be set to 1. But if Vin < VDAC then current bit will be set to 0 and next higher bit will be set to 1. I hope, it will clear your doubt.

[@jayaprasadb2044]

Here what is the use of Vref

[@ALLABOUTELECTRONICS]

The reference voltage will decide the full scale range of the input voltage.

[@nehajose6843]

2.40 how did the voltage became 12v

[@dora9103]

great video, I have a question which is what is a sample? is the output from DAC makes 1 sample?

[@ALLABOUTELECTRONICS]

Sample is one sample output of the sample and hold circuit. The actual signal that is fed to the ADC is real time signal like a voice signal. The ADC can not convert the conversion instantaneously. According to its conversion time, the sample and hold circuits takes the sample of the real time signal . It is basically a some voltage. That is voltage is fed to ADC and then ADC converts that voltage to digital code. I have explained the entire procedure in the introductory video on ADC. Please check this video for more info. kzbin.info/www/bejne/fprGi5admayrkLssi=4g0hsR0sxwE_Zma6

[@dora9103]

@@ALLABOUTELECTRONICS got it! Thanks so much!

[@adels8205]

Why will be the corresponding voltage half of the Vref?

[@nonikamboj3619]

what is we use the formula (V in/V ref)* 2^3 which would give (11.2/16)* 8 = 5.6 which ain't 1011?

[@aarifahhz1043]

hello sir, do i need to complete the iterations according to the number of bits. (let say i am using 4bits, so i need to finish the iterations up to 4 clock cycle, till all the possibilities in the range of 0 bits to 15 bits) or i need to refer to the Vdac that i want convert and stop the iterations. please help me, anyone? i got confused........

[@ALLABOUTELECTRONICS]

For N- bit successive Approximation ADC, the conversion time will be N x Tclk. Yes, that is means for 4 bit ADC, in four iterations the signal will be converted into corresponding digital code.

[@ratneshgupta271]

Please explain what is the meaning of DAC ref voltage and where clock will be applied?

[@ALLABOUTELECTRONICS]

Similar to ADC, DAC also requires reference voltage. Based on that reference voltage, the DAC will generate the output voltage for the specific code. Please watch the earlier videos on ADC and DAC playlist for more information. Here is the link for the playlist: kzbin.info/aero/PLwjK_iyK4LLCnW-df-_53d-6yYrGb9zZc

[@baswarajsghali2074]

How cycle latency of sar ADC is zero when it takes N cycles for N bit conversion?

[@ALLABOUTELECTRONICS]

N cycles are clock cycles. Here the latency refers to the time on top of the expected conversion time. which is defined in terms of the data cycles. Yes, that's true that it takes N*Tclk for the conversion. So, the 1 data cycle for N-bit SAR ADC is (N*Tclk + some delay ) If the data is available after that immediately, then it is 0 cycle latency. If you see, in case of the pipeline ADC, the acquired data of the Nth sample might be available after N+1, or N+2 data cycle. So, it can be said that it has 1 or 2 cycle latency. I hope it will clear your doubt.

[@KennethAnderson-ts3zq]

8:20 why do we say typically SAR adc has 0 latency. It requires N Tclk cycles to convert right ?

[@ALLABOUTELECTRONICS]

Here latency refers to the conversion cycle and not clock cycle. The one conversion cycle is equal to N x Tclk. In the SAR ADC, since the conversion gets completed in the 1 conversion cycle only, so it has zero latency. In pipelined ADC, it takes more than one conversion cycle. I hope, it will clear your doubt.

[@KennethAnderson-ts3zq]

@@ALLABOUTELECTRONICS Yes, clear now. Thank you so much ..

[@World_Theory]

Can the design philosophy of the SAR and Flash ADCs be combined, to create a hybrid ADC that has a reduced cost compared to a comparable Flash only ADC, by sacrificing just a little bit of latency? What I mean is, using, for example, a 7 bit Flash ADC for one step in the SAR process, and then doing it again, to create a 14 bit total digital value to represent the analog input voltage. Is there there some problem with this, that's obvious to someone more experienced?

[@ALLABOUTELECTRONICS]

Yes, in fact, such hybrid ADCs are available. (Also known as Sub-ranging or half flash ADC) One such ADC is MAX 153. Anyway, I will cover it soon in the next video.

[@World_Theory]

ALL ABOUT ELECTRONICS, I'll look forward to your next video, then!

[@kumarsamaksha7207]

god level video

[@vengalrao5772]

I watched thrice . I got it

[@Sirifactstelugu]

Can u explain A PLL is designed with an input frequency of 2 MHz and output frequency of 2 GHz

[@ALLABOUTELECTRONICS]

I have already video about PLL. please check this video. kzbin.info/www/bejne/h2bHdGyKl9-Fb80

[@World_Theory]

I don't know if this is actually what it going on, but is your audio clipping a little bit? Are there peaks in volume on certain phonetics, that are too high for your microphone to record? I don't know if moving your microphone just a tiny bit away would help; you might just have a low quality microphone for all I know, and it's not actually clipping that I'm hearing. But I like to think of recording audio like cooking food; volume is salt, the recording stage is when you throw the ingredients in the pot, so you can always add more volume/salt after your food/audio is recorded, but you can't take it back out. (I'm sorry for that painfully bad analogy…)

[@somewherelost5068]

Lol

[@mancity5179]

@@somewherelost5068 lol

[@shreyaroy1707]

Hi, in 01: 40 you explain the corresponding Vdac to be 8 volts using a formular = Vref*( B0/16 + B1/8 + B2/4 + B3/2). Could you please tell me where you got that formular from? I don't udnerstand that bit

[@ALLABOUTELECTRONICS]

Please check this video on R-2R ladder type DAC. At the later part of the video, I have explained that. If you go through this video, you will get it. Here is the link: kzbin.info/www/bejne/hpSUknmipN2Gg9k

[@A.Jaishankar]

What is inside control logic circuit and SAR block? Please help me.. I'm stuck here in my project....🙏🏽🙏🏽

[@deepikagupta8816]

Sir is this synchronous sar adc or asynchronous?

[@RushilChopra101]

How did we get the corresponding output voltage 8 please tell

[@ALLABOUTELECTRONICS]

Would you please mention the timestamp, where you are referring to in the video.

[@RushilChopra101]

@@ALLABOUTELECTRONICS I got it sir but thanks for asking 🙏

[@kenilbalar707]

What is role of sample and hold circuit here?

[@pavankumarmeda7348]

How SAR is 0 latency as it is taking n number of cycles for the conversion right? Can you please explain?

[@ALLABOUTELECTRONICS]

As I mentioned at 8:00, here latency refers to the conversion cycle. SAR takes n clock pulses for conversion. So that refers to 1 conversion cycle. And since data is available immediately after the conversion cycle, it can be said that it’s latency is 0 cycle. But if you see the pipeline ADC, the data of one conversion is available after couple of conversion cycles. ( for example, nth conversion is available after the completion of n+2 conversion cycle) so in such case, it has latency of 2 conversion cycles. I hope, you understood the difference between conversion cycle and conversion time.

[@pavankumarmeda7348]

Thank you for the detailed explanation

[@healingraion453]

Hello I have a question, what if the Vref was 11? What is gonna be the Vin then?

[@ALLABOUTELECTRONICS]

If Vref is 11V then your input can't be more than Vref. In that case, it has to be lower than Vref.

[@anabhayansp7742]

@7:55 how do you define a conversion cycle

[@rahmatramadhan6356]

how if Vin = Vdac at B1? how to set B1 dan B0?

[@user-zn5du6je4q]

I believe that 1 0 0 0 will output not 8V but 8*(16v/15) or 8*LSB (least significant bit)

[@ALLABOUTELECTRONICS]

No, that's alright. For 1000 it will be 8 V and similarly for 1111, it will be 15V. You may check the equation for the output of the DAC at 1:40.

[@user-zn5du6je4q]

@@ALLABOUTELECTRONICS Thank you for your response! But shouldn't a DAC with all input bits equal to '1' output their reference value/voltage (in this case 16v)?

[@ALLABOUTELECTRONICS]

DAC full scale output voltage is 1LSB less than the reference voltage. I think, in one of the DAC video, I have also mentioned that. That is why, from the DAC expression mentioned at 1:40, you are getting 15V when all bits are 1. (1 V less than Vref) I hope, it will clear your doubt.

[@hole386]

How can the SAR ADC have 0 latency when it takes N clock cycles to converge the result

[@ALLABOUTELECTRONICS]

Here the latency refers to the delay between each conversion. N x Tclk is the conversion time. But after that conversion time, the output is readily available. It means it has 0 latency. If the output of this conversion is available after the delay of one more conversion cycle, it means the ADC has a latency of 1 conversion cycle. I hope, it will clear your doubt.

[@ALLABOUTELECTRONICS]

If you now watch the video from 7:35 onwards then you will get it.

[@hole386]

@@ALLABOUTELECTRONICS gd bro the customer service, that clears it up, thank you for making these youre the GOAT

[@jayaprasadb2044]

Do we need it

[@pratikkaul77]

It's searching a binary tree.. For the DSA folks 😃

[@sanskarvidyarthi9895]

What if Vdac = Vin?

[@JennyTheBear]

Can you do for Sigma delta ADC

[@mxnthan_]

Akash EEE🔥