Types of PCB Grounding Explained | PCB Layout

Tech Consultant Zach Peterson explores the different types of ground PCB designers might come across in schematics, datasheets, reference designs, etc. He dives deep into PGND, AGND, DGND, SGND, and more so you can learn how to have a consistent ground potential in the midst of all the varying connections.
0:00 Intro
0:48 DGND, AGND, SGND, & PGND
4:16 Analog-to-Digital Converter (ADC) Example
8:00 PCB Layout Example
10:29 Net Tie Location?
12:33 Power Converters
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👉 Should You Use Star Grounding for Analog and Digital Ground Separation?: resources.altium.com/p/how-to...
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[@zoa_photo]

This was absolutely not the content I was searching for but I have no regret having listened to every seemingly wise word you just said. Thanks a lot !

[@AltiumAcademy]

So glad you enjoyed it!

[@myetis1990]

Hey Zach! I'm used to answering my questions, but now I can't keep up with you since you answer my questions without asking them :)) thanks a lot for the video

[@BillySugger1965]

I *SO* concur with your uniform ground approach in all mixed technology cases except where there are specific reasons. Split grounds and net-ties are a nightmare to get right and in my experience cause FAR more EMC issues than they avoid. Proper circuit and trace segregation is definitely the way to go, and is why careful component placement is such a key step before going anywhere near a routing tool. And with things like switching regulators, I keep the close-coupled, high current paths as short and wide as possible on the component layer, (another trick to perform during placement), keeping trace impedance minimised and avoiding vias in those paths at all costs. Once power rails have been sufficiently decoupled on the component side, I then route the rail to a split power plane or a trace network as the design requires. Keeps EMC controlled, improves performance and aids thermal management. What’s not to like?

[@akbf007]

Guys it really works, I checked

[@1simc1]

Thanks Zach, love your content!

[@AltiumAcademy]

Glad you enjoy it!

[@26A814]

Hi, thanks for your video! I have a question, there are some circuits that has Field Ground. how can I layout that?

[@Karthik_Selvam]

Really nice video to understand the concept about GND. Looking forward to your next video

[@AltiumAcademy]

Glad to hear that

[@tr3kn3rd]

Awesome video, thanks for the content. Good rule of thumb to implement split planes for low frequency applications. Also to add that for large current applications this becomes quite important. Example I keep the return paths for a motor driver completely isolated from my ground and use net ties to avoid introducing offsets when my motor is running which can be quite large.

[@AltiumAcademy]

Glad it was helpful!

[@ANTALIFE]

Absolutely agree that you should never split your PGND/DGND/AGND (aka 0V), otherwise you are asking for trouble when you go through EMC/EMI testing If you are worried about signal noise then segregate your circuits, as in move the power supply to one corner of the board, the digital section to another, and the analog section to another again. Then when you transition from one EM zone to another (say analog to digital), you add some inline filters at the EM zone boundary

[@vinayakonimani7628]

Im a student in electronics and communication engineering. Thanks for your advice, noted it down.

[@hiteshjangra81]

its there is any way to control the switching noise in PCB?

[@andrasparanici5491]

I had a project where I had multiple type of GNDs (SBC GND, MGND, AGND, DGND, OSCGND etc) but eventually they were all connected together to the main GND using - as we call it - a starpoint (something like a "net tie"). 6L board. On one of the layers was the split and connection multiple GNDs, on another one a complete GND fill.

[@Zachariah-Peterson]

At that point you basically just have 1 oddly shaped ground conductor. No problem with that as long as you route over it correctly (only over ground). Rick Hartley will disagree with me until I start showing him some strange board shapes and draw out the area where routing is confined.

[@BHBalast]

Good topic for beginners, great pick. :)

[@AltiumAcademy]

Glad you think so!

[@McCaffreyJohn]

It worked! Tank you sir.

[@AltiumAcademy]

Glad it helped

[@kacperbardecki3671]

Thank you

[@JoannaPirieHill]

You can have as many "Ground" nodes as you want below 100 KHz. But to pass EMC / EMI requirements you only get one RF ground above 100 KHz. You pass EMC / EMI by designing controlled impedance transmission lines for each and every signal that has intended or unintended content above 100 KHz. Splitting or cutting up ground reference layers are the single most common cause if EMC and EMI failures. You keep noise current out of sensitive signals by designing the transmission lines, not by cutting up your RF ground.

[@cvillafane4694]

it does not only depend on the frequency, it depends on the rise / fall times. Current ICs have rise / fall times of pico sec and can cause emi / emc problems EVEN at low frequencies. There are interesting notes from Eric Bogatin and Rick Hartley on this.

[@Zachariah-Peterson]

I've said a variation of this in just about every video I've made on high-speed design and grounding, including this one

[@JoannaPirieHill]

@@cvillafane4694 To make any AC signal requires frequencies. For a pure tone there is only one required. For a digital signal made up of rising and falling edges there are many frequencies spaced at the period of the signal. The fidelity of the transport of these signals depends on the amplitude and phase delay distortion of each of these signal components at all of the various frequencies.

[@seinfan9]

Well, he explains in the video that high speed transmission lines have a well defined reference path that follows the trace closely. Additionally, he also said that split ground planes can be implemented properly and is preferable when the analog signals are low frequency. So your information doesn't contradict what was presented in the video.

[@Zachariah-Peterson]

​ @Plissken The key here is the "how" part of doing that properly. Most people don't do it properly and they try to do it when it is not needed. Audio is one example, but part of the reason for that is that sometimes your audio system will be galvanically isolated from your codec and speaker or transformer driver/amplifier, so you're forced to split things. Another instance if when your signals are very low level, like SNR ~ 1, in which case you also need to maintain isolation. You could do it with a galvanically isolated ADC, very tightly coupled transformer, or an optocoupler all with a very tight loop into your ADC. Similar idea going in reverse from a DAC.

[@fairuzahmadnaufal4196]

Awesome videos, easy to learn. It's easy to understand and why the gnd pcb design is really complicated haha

[@AltiumAcademy]

Glad you think so!

[@coderebel3568]

How about ground for an audio codec like the AD1937? I did it with a separated ground and only routed digital lines over the dgnd and had an optional net tie with a junper, close to a 2x4 pinsocket which had the AGND and DGND nets connected with nice thick traces to their respective copper pours. I still had analog output garbage that could have been caused by EMI. Unfortunately I don't have equipment to measure EMI. I only have a kind of decent scope and an average multimeter. Maybe I'm just biting off more than I can chew here though 😅

[@adtelectronics1273]

Hello, thanks for your work! Can you make video about hatched polygon, about it's usage and benefits?

[@Zachariah-Peterson]

We recorded this and it is in editing now

[@varunshahi9026]

Instead of using a net tie I used a zero-ohm resistor to connect PGND and AGND. I think that it is the similar way to do grounding in a dc-dc non-isolated converter.

[@Zachariah-Peterson]

Yes net tie and zero-ohm resistor are the same in this case for non-isolated converters. I think a zero-ohm resistor is simpler for routing just because you now do not need to create a specific net time component and the system will automatically separate the nets by name.

[@ltlt6117]

Hi Can we use net tie for pcb with some high voltage blocks and some digital blocks???

[@VikashGupta-vb9bl]

Different types of isolated pattern layout in pcb design and how to control during pattern plating was not excced pleass explain.

[@WeirdGabriel5]

Very helpful

[@AltiumAcademy]

Glad to hear that

[@bernard.tomasevic]

In the buck converter example, could we have one ground net for these two separate grounds (pins) but carefully layout the pulsed current part (SW node) away from the rest of the circuitry?

[@Zachariah-Peterson]

Sure you could, but the best strategy for SW node layout is with short connections. The reason is that the connections have their own loop inductance that can generate or receive EMI. That loop inductance is usually something like 5 nH/inch.

[@losaminos59]

How about for a battery source (floating) with high DC voltage output using a transformer like the xenon flash capacitor charger like the LT3751? Their reference design on the datasheet shows a separate analog and digital ground areas on both the schematic and pcb drawings. I've read your blog post about the different grounding options for PSU but I'm not sure how to implement it on a battery source. Since I don't have an earth / chassis connection, would it still be ok or not, to connect the xformer primary ground with the secondary ground using Y capacitor to decouple the HF noise back to the primary gnd? Or should I just separate the two ground areas completely?

[@Zachariah-Peterson]

The reason there is separate grounds on the LT3751 reference design is because that system is a flyback controller, which uses a transformer. While there is not necessarily a requirement to use separate grounds on each side of a transformer, one of the reasons you would use transformer is to implement galvanic isolation, and since you are using a high DC voltage source you want to have that galvanic isolation with two different grounds on each side. Since you don't have an earth/chassis connection it is still okay to do the connection with the Y capacitor, in fact I would recommend trying this and examining high-frequency emissions from the system. You have to be careful with leakage across that capacitor though. If you have high leakage then you might cause annoying shocks at any HMI element in the design (buttons or connectors), there are EMC standards that specify limits on this type of ESD through leakage.

[@SamuelPotancok]

Hello Zach great video! So what about mixed signal PCB with 6 ADC, 3 of then on main PCB and rest of then on secondary PCB connected through connector. I need split GND and AGND on both PCBs so where I have to connect grounds together?

[@BHBalast]

Great question I'd say it depends if you have isolated communication, or/and power and differential analog or digital signalling, but in the most cases, it'd be better to connect both grounds together. When deciding what you should do you must look at the return currents of your circuits elements/subcircuits, if you can imagine all of them, I'm sure you can decide what's the best solution for your circuit.

[@robiniddon7582]

What sample frequency do the ADCs run at/what frequency is the signal you are sampling? Is the reference voltage for the signal you are sampling the same for all 6 ADC? The most sensitive signal is probably the one you are sampling? Do you need to pass EMC (is this a product or a hobby?)

[@breedj1]

Never ever use split grounds if you do not need isolation. Look at Rick Hartley's and Eric Bogatins video's. They have a joke at the EMI test houses. 'What kind of people use split grounds?... A customer.' kzbin.info/www/bejne/r4TYho17n6aFhrs

[@robiniddon7582]

@@breedj1 unless the frequency of the signal in the analog part of the circuit is low, like audio frequencies. The return currents for such low frequency signals spread far and wide, they do not stick to the signal path. If they spread so as to be close to your fast digital signals then you will get noise in the analog section. How much? It depends 😜. But if you are sensitive to microvolts then very likely you will have to prevent the analog return paths straying into the digital area and the only way to do that is to separate them.

[@breedj1]

@@robiniddon7582 Have a look at the video it is very interesting. It shows that at around 2kHz the return currents are already taking the path below the trace. There is no benefit in using separate ground planes.

[@jessstuart7495]

Common mode noise/interference is the enemy. The amount of noise/interference coupled into your PCB by signal and power supply wiring (antennas) will often swamp the amount of noise/interference coupling on the PCB itself. Use ferrite beads liberally.

[@dariodraiman6339]

I understand you need common mode chokes in the input of the circuit to deal with common mode noise. Ferrite beads would work for differential mode noise.

[@MERyan-lo5vt]

thanks, it is unclear for me tge last example, i couldn't notice the part where the onchip gnd is connected to PGND.. could you please clear it a bit, thanks

[@unicode_string8341]

I think this video is VERY helpful to me as I am suffering some very serious ground noise inside my ADC board. I'm using FPGA to drive my AD9826 to receive voltage data and I use one single ground as the datasheet told me. But then I found the noise on the ground very high which interrupt the analog signal (in my case, the frequency of the analog signal is very low), do I need to seperate the ground and USE a piece of Ferrite bead to block the clock noise? And if the frequency of the input signal becomes higher (about serval MHz), what should I do to reduce the noise?

[@unicode_string8341]

Also, if I have several device like this, is making more than one ground connection a good choice?

[@Zachariah-Peterson]

Maybe I can help you by doing a video demonstrating how to route it correctly....

[@jacobfaseler5311]

In some ADC applications I’ve seen the recommendation to connect analog ground to digital ground through a pi filter. Pros / cons?

[@BillySugger1965]

I would say definitely not! The aim should be to keep grounds together in terms of voltage, and increasing the impedance between ground nets only encourages ground bounce between the nets. The best place for a pi-filter is connecting the supplies, between DGnd and AGnd, with the capacitor each side connected as close to the respective Gnd pin of the interfacing chip as possible.

[@Zachariah-Peterson]

No don't do this, it really is better all around to just use continuous ground unless you have a reason not to. @blue5375 mentions ground bounce between the planes, I think he is referring to the fact that the disconnected ground regions can have a potential difference (voltage) between them. The result is that if the potential between those regions starts oscillating, then you have a changing electric field between them that starts radiating, and you have basically created two big edge-coupled patch antennas. One reason to use different grouns is, for example, with use of an isolated ADC, which requires split grounds but the purpose is for galvanic isolation. I just finished a tutorial with this type of design, you can find the source files on my company website (search for Northwest Engineering Solutions and go to the Design Examples page under the Resources tab).

[@hoomanbadieimoghadam1994]

i want to suggest you , maybe it will be more helpful if you show the effect of separated gnd with animation or Simulation , to understand what will be actually happened to separated gnd in facing with noise , this is somthing that literally confused us in Connecting GNDs Together and the location of this connection .

[@Zachariah-Peterson]

I believe I have shown some simple examples of this in other videos. But in any case I will see about creating an example, possibly in OpenEMS.

[@alaaashraf8472]

Hi, I don't understand why we need a net tie in the buck converter with the via. I think via connection is a single point anyway, right ? 16:29

[@Zachariah-Peterson]

It's not a strict requirement. Technically because the PGND and GND pins are being connected with a piece of copper, they will have the same ground potential. The reason this is sometimes done is to control return currents in the plane layer; it enforces some isolation from nearby currents so that they do not interfere with the voltage measurement in the feedback line, and we would like for the feedback line to be either noise free or to only reflect the noise on the power bus in order to provide compensation through the converter's feedback loop. If the insulator layer is much thinner, then you can get away with using a complete piece of ground for your buck converter because any signals that might induce noise on that feedback line will have a more strongly confined distribution of their return current below the trace. It's equivalent to reducing crosstalk between the FB line and some other line.

[@alaaashraf8472]

@@Zachariah-Peterson seems to make sense now. thanks for your reply

[@torbenbrokate5714]

I also like one single Gnd for all. Came to that with 3 ADCs on one board, so where to place the NetTie (close to ADC, yes, but wihich? ;) )

[@Zachariah-Peterson]

Exactly... And some ADCs don't even have separate AGND and DGND pins, it's just a single GND pin. What do you do in that case? Hint: just use a plane!

[@BillySugger1965]

Make the whole ground plane the net-tie 😉

[@lolsypussy]

Can I use a null resistor as net tie?

[@Zachariah-Peterson]

I've never done it but technically you could do it.

[@JonathanDFielding]

ugg, GND islands are such a disagreeable topic. As much as I know that return currents can be controlled in placement, I still prefer to carve out AGND separately then use a large Net tie. Once a signal from a sensor, that was on the regular GND, comes into a high impedance input of an op-amp, that's when I consider the signal now on and around AGND. I usually will place my net tie between DGND and AGND right under or around the ADC/DAC or Micro Controller and I'll route the analog signals around the AGND. Will you explain any holes in this logic? Not using this old school tried and true way is really hard to break, even when I know it can be done with proper placement and routing.

[@Zachariah-Peterson]

If you're only keeping the digital stuff in the digital area and the analog stuff in the analog area, and if you can guarantee the digital circuits are completed in the digital section and analog circuits complete in the analog section, then you've basically created an isolated system and the net tie becomes kind of meaningless. In some ways, the net tie is already meaningless because in a non-isolated ADCs the component links the GNDs on the die anyways, the exception is when the ADC is a galvanically isolated component. But with modern ADC packages or an MCU, you might have signals that must route over ground but they can't because of the split. I'm sure you could find some components where the interfaces are separated like you suggest but it is not always like that, just look at mixed signal ASICs or MCUs in quad packages. I think the biggest problem with the split AGND/DGND guideline is that newbies see it and they don't understand that they shouldn't route across the breaks in ground, but then they do it anyways. Then they wonder why they have excess radiation or fail susceptibility testing.

[@jimjjewett]

When talking about *where* to put the net tie around kzbin.info/www/bejne/Z2q6n4yGnbOCfpI ... I missed the answer. As best I could tell, anywhere along the boundary should meet the 0V requirement in theory, and in practice, it seems you would want to be farther away from the chip, since that is something which could temporarily change that. A minute later, when talking about low-frequency analog signals that spread out, I would expect that you want the net tie to be as far as possible from those signals. But you suggested being near the chip, and relatively (given the boundaries) near the analog signal line ... what did I miss?

[@Zachariah-Peterson]

Actually I'm arguing that if you lay out the board properly then you don't need the net tie at all. If you look at these kinds of recommendations they will put it near the chip or directly under the chip. In the case where you can't control return paths or noise coupling, and then you start splitting GNDs, I think it's much better from a noise perspective to take an isolated design approach but that is much harder, now you have to worry about inductive or optical coulping across ground regions. If you do it wrong you'll have floating grounds that then radiate, it's a pain to do it correctly and it can make the rest of the layout harder.

[@jimjjewett]

@@Zachariah-Peterson So the real answer is that you should separate things by enough that you can do it as a single plane, and if you can't do that, try to isolate them completely, and if you can't do that, try to use a single net-tie, but you're already at 3rd-best, so worrying about *where* to put the net-tie is spending your optimization time on the wrong thing? And if you need a rule of thumb even for that, do whatever is conventional and won't make people curious, which often means "near the chip"?

[@Zachariah-Peterson]

@@jimjjewett ​If you're at the 3rd best solution then you've probably optimized the wrong stuff and put yourself in a corner where you're now forced to use a net tie instead of a single plane. At that point, might as well near do it the chip I and throw a wonky looking gap between your digital stuff and your analog stuff, but prepare yourself for excess noise!

[@user-ww2lc1yo9c]

music is not necessary