Understanding Von Neumann and Harvard Architectures | A Side-by-Side Comparison

In this video, we explore the differences between Von Neumann Architecture and Harvard Architecture, two fundamental computer design approaches.
Von Neumann Architecture is the traditional approach used in most computers. We explain how it organizes memory and processing units, with instructions and data stored in the same memory space. We discuss its advantages and limitations.
Harvard Architecture takes a different approach, utilizing separate memory spaces for instructions and data. We highlight its unique characteristics and applications in specialized fields.

[@ArneChristianRosenfeldt]

Can you explain why on the Jaguar Atari had no problem to make hard decisions and dedicate a fixed amount of on-chip memory to the line buffer and palette ( Harvard like ), but felt the need for von Neuman architecture for JRISC ? Or would you say that with the advent of on-chip scratch pad memory + external memory, the programmer decides where to put code and data?

[@OhmazingPhysics]

I agree with you that the Atari Jaguar had a hybrid memory architecture, with some Harvard-like features and some von Neumann features. The line buffer and palette were dedicated fixed-size on-chip memory that was only accessible to the graphics processing unit (GPU). This was a Harvard-like feature, because the GPU had its own separate memory space for code and data. The JRISC CPU, on the other hand, shared the same memory space with the GPU. This was a von Neumann feature, because the CPU and GPU could both access the same memory locations. There are a few reasons why Atari may have chosen to use a hybrid memory architecture on the Jaguar. First, having dedicated memory for the GPU allowed it to access its data more quickly, which improved graphics performance. Second, having a shared memory space allowed the CPU and GPU to communicate more easily, which made it easier to develop games that integrated graphics and gameplay. Finally, using a hybrid memory architecture allowed Atari to use less expensive memory chips, which helped to keep the cost of the Jaguar down. With the advent of on-chip scratch pad memory and external memory, the programmer does have more control over where to put code and data. However, the decision of whether to use a Harvard or von Neumann architecture is still up to the system designer. There are trade-offs to consider, such as performance, flexibility, and cost.

[@ArneChristianRosenfeldt]

@@OhmazingPhysics I love harmony and would have liked to see the best of both worlds. I am a coder and Bad at naming variables. But I imagine that with the relative low clock speed of 28 MHz in combination with high bandwidth interconnect on a die we could have had speed and flexibility. A 8x8 Matrix of interconnects maybe don’t add much latency to address generators. Thus we would have 7 internal memory banks plus external memory. A collision may be detected within a cycle. It blocks write enable and returns all address lines from the colliding processors to highZ to end the short circuit. Ah I see. Probably we need to guess which bank each processor will access next ( stay in its bank ). Then detect if it switches a bank, then insert a priority circuit to resolve collisions. This will add one cycle latency? Atari claims that they can resolve bus priority within a single cycle. The C64 resolves sprite priority at 8 MHz. Probably a lot of coders will be confused when the compiler moves some buffers a little bit ( reaching into the next bank ) and suddenly their frame rate drops. 32 bit data and 16 bit address (SRAM needs 9 bits and DRAM is multiplexed) gates sound like a lot. The 8x8 interconnect Matrix is regular and can be shrunk to a small size. Transistors can be placed in some interleave pattern. Surely, it will eat into the real estate of the actual SRAM ( also Matrix shape ). Jaguar has some 64 bit DRAM interface. I guess that the z buffer would really love to read z, compare, write (prepared) z and pixels at full width ( pixel precise write enable) without serialisation ( be done with it ). All others get 32 bit serialised access ( clock rate of DRAM is half that of that of SRAM ). Z buffer owns the DRAM … Still won’t work. Compare needs a cycle. Could just as well serialise and hide the cycle there. Just make sure that for random 32 bit access the correct word is selected by the memory controller from the 64 bit and the other is cached “read ahead buffer “. With more RnD budget the z buffer would read ahead one phrase…

[@stachowi]

Modern CPUs use both architectures.

[@OhmazingPhysics]

Thank you for your comment! I appreciate your interest in computer architecture. Regarding your comment. That's not quite accurate. Modern CPUs use a modified Harvard architecture, which combines elements of both Von Neumann and Harvard architectures. In a pure Von Neumann architecture, instructions and data are stored in the same memory, and the CPU uses a single bus to access both. This can lead to bottlenecks, as the CPU has to wait for the memory to finish transferring data before it can fetch the next instruction. In a pure Harvard architecture, instructions and data are stored in separate memories, and the CPU uses separate buses to access each. This eliminates the bottleneck, as the CPU can fetch instructions and data at the same time. However, there are some disadvantages to a pure Harvard architecture. First, it is more complex to design and manufacture a CPU with separate memories and buses. Second, it can be more difficult to write code for a CPU with a pure Harvard architecture, as the programmer has to be aware of the separate memories. For these reasons, modern CPUs use a modified Harvard architecture. This architecture combines elements of both Von Neumann and Harvard architectures. The instructions are stored in a separate memory from the data, but the CPU uses a single bus to access both. This eliminates the bottleneck of a pure Von Neumann architecture, while still maintaining the simplicity of a pure Harvard architecture. The modified Harvard architecture is used in most modern CPUs, including x86, ARM, and PowerPC. It is a good compromise between the performance and simplicity of Von Neumann and Harvard architectures. Once again, thank you for your comment and I hope this explanation clarifies the topic for you. If you have any further questions, feel free to ask.

[@0xD1CE]

@@OhmazingPhysics "This architecture combines elements of both Von Neumann and Harvard architectures." ...So as the OP was saying, it uses both architectures. Going to be honest, your reply almost seemed AI generated from some of the explanations. "The instructions are stored in a separate memory from the data, but the CPU uses a single bus to access both. This eliminates the bottleneck of a pure Von Neumann architecture, while still maintaining the simplicity of a pure Harvard architecture." They are stored in the same memory but placed in different cache. That's what a modified Harvard architecture is. You also literally stated earlier that Harvard Architecture is more complex so what do you mean by "maintaining the simplicity of a pure Harvard architecture."???