USB low level debugging, feat. sigrok and OpenVizsla

This video quickly introduces various way to perform USB low level debugging.
Some of the projects / boards used :
- sigrok / pulseview : sigrok.org/
- saleae : www.saleae.com/
- icebreaker : www.crowdsupply.com/1bitsquar...
- iua : github.com/smunaut/iua
- OpenVizsla : openvizsla.org/ ( available here : shop.sysmocom.de/t/usb/tracer-... )

[@pixelflow]

Great breakdown, and kudos for all the different price point and technical approaches!

[@0xssff]

[@bennguyen1313]

Any thoughts on the USB that's on the Fomu / TinyFPGA boards? It seems like it instantiates a RISC-V softcore processor on the Lattice (ICE40UP5K) that runs MicroPython (FuPy).. but not sure how the USB Bootloader/stack actually works. What's the (lite-x?) usb ip interface that allows the communication to the host?

[@smunaut]

Sorry I don't really understand your question ... The fomu uses a USB core implemented in the FPGA itself, it appears to the RISC-V softcore pretty much the same way as any USB device core appears to the CPU in any microcontroller with USB, you have control register and buffers or someway to send / receive USB packets. There are several of such USB core for FPGA. The one used in the FOMU official bitstream is ValentyUSB ( github.com/im-tomu/valentyusb ). I also wrote one myself available at github.com/smunaut/ice40-playground/tree/usb/cores/usb that I used on the fomu and other ice40 boards.

[@slashghero]

Hi, could you post link for that green development board with SIM slot.

[@smunaut]

It's a SIMTrace2 board : shop.sysmocom.de/products/simtrace

[@J-K-AG]

How do you get the data the actual from openvizsla?

[@smunaut]

I was using github.com/openvizsla/ov_ftdi but now there is also github.com/usb-tools/ViewSB which support the OpenVizla

[@J-K-AG]

@@smunaut brilliant thank you so much