Verilog Code Of Single Port RAM with Synchronous READ/WRITE

[@ShivamKumar-ox1vy]

Great explanation....

[@achyuthanand4391]

What is oe_r doing in the Design?

[@ZakirHussain12345]

What is the difference between Single port RAM and Dual port RAM???

[@digital2realtutorials671]

Give me some time, I will reply back to you with proper answer.Thank you.

[@ZakirHussain12345]

@@digital2realtutorials671 Thank you for your reply. I will wait.

[@digital2realtutorials671]

In single port RAM, RAM supports sequential Read and Write operations but not simultaneously. That means only one operation is possible at a time, be it READ or WRITE. Single port you have here, RD/WR Address, single write enable for read and write. One write bus and one read bus. Now in asynchronous dual port RAM, two separate ports are there , let's name it Port A and Port B. Each port will have respective address lines , control lines and I/O lines(READ data bus and WRITE data bus ). Now in synchronous single clk dual port RAM design , any combination of independent read/write operations in the same clock can be done. The Dual rate dual port RAM supports simultaneous READ and WRITE operations to different addresses at two clock rates.

[@ZakirHussain12345]

@@digital2realtutorials671 Thank you so much. 🙏 . It helped me.