Verilog Design, Simulation & Synthesis of Round Robin Arbiter | Hardware Design | @vlsiexcellence

[@chrisbspear]

But wait, it gets worse. You said there is no priority. Start with req = 1111, 0000, 1111. gnt should go 0001, 0000, then 0010. But since your design sets next=IDLE when req=0000, the arbiter 'resets' back to Idle, and always starts by looking at req[0], the lowest bit, instead of starting where it left off, req[1].

[@pabhiram1]

The design is not correct. In the verilog code the gnt only depends on the present state and does not even check which client has request

[@tanujicr]

This design will have starvation issue and the whole point of a RR arbiter is lost

[@dakshit1276]

link of program