Verilog HDL Project | Round Robin Arbiter(with code) | EDA Playground | Verilog

In this Verilog project, we will discuss and implement Round Robin Arbiter in Verilog HDL. It has been written and simulated by Mr. Aditya Mehta in an online simulator EDA Playground.
Please find the Verilog code below: github.com/Arjun-Narula/Round...
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#verilog #verilogproject #arjunnarula #electronic
0:00 INTRODUCTION TO THE CHANNEL
0:07 INTRODUCTION TO THE PROJECT
0:30 ARBITER AND IT'S USES?
2:50 ROUND ROBIN SCHEDULER
7:01 ARBITER GENERAL TOPOLOGY
12:49 STATE MACHINE
14:06 TIMING WAVEFORM
15:42 VERILOG CODE

[@ArjunNarula1122]

Please find the code in the link description. Any suggestions or queries are most welcomed. PLEASE SUBSCRIBE TO THE CHANNEL. Other Projects- ►Traffic Light Controller in Verilog - kzbin.info/www/bejne/j6Wan6Jsp9x2jM0 ►Round Robin Arbiter in Verilog - kzbin.info/www/bejne/jmfSe6Ftp55gbtU ►Vedic Multiplier in Verilog - kzbin.info/www/bejne/bH6Wn6yvhsujfrc ►Clock with Alarm in Verilog - kzbin.info/www/bejne/poXOYntrZcprmKs ►Washing Machine in Verilog - kzbin.info/www/bejne/n3LSmmygid-rmas ►N bit Multiplier in Verilog - kzbin.info/www/bejne/op7ddJeua8yemrc ►PWM Shift Register in Verilog - kzbin.info/www/bejne/hqucpIOcobCjjsU ►Vending Machine in Verilog - kzbin.info/www/bejne/qnvGYZWid6mFsNE ►Hexadecimal Keypad Scanner in Verilog - kzbin.info/www/bejne/j2LGoWWhrNSma68 ►RAM - ROM Design in Verilog - kzbin.info/www/bejne/o2Kbiohvrc94irc

[@harshitsingh480]

have you done rtl synthesis and rtl to gds flow of it? need some help of yours in layout

[@yuganshibharti3892]

Explanation and presentation is phenomenal!! Awesome work guys 🔥🔥

[@ArjunNarula1122]

Glad you liked it Yuganshi !!😊

[@atushgoel7823]

Great work Arjun and Aditya

[@ArjunNarula1122]

Thanks ✨✨

[@ishajain949]

Amazing work ✨ Great explanation of every aspect of the project Aditya✨ Great channel Arjun 💯

[@ArjunNarula1122]

Thank you for the appreciation Isha!!😊😊

[@ayushmahendru1858]

Amazing project guys!!

[@ArjunNarula1122]

Thanks Ayush!!

[@divanshubansal2474]

Too goood. A well explained and unique project

[@ArjunNarula1122]

Thanks Divanshu !!😊

[@parashgoswami7561]

Keep up the good work guys 👍🔥

[@ArjunNarula1122]

Thank you Parash!!!

[@sarthakwali1210]

Great and well-explained content!

[@ArjunNarula1122]

Thanks Sarthak!✨

[@sumantpathak7151]

Great one! Op! 🔥

[@ArjunNarula1122]

Thanks Sumant! ✨

[@shamanthkolli2214]

Great Content , Well simplified !!!

[@ArjunNarula1122]

Thanks Shamanth ✨✨

[@tanishgarg2574]

Great explanation 🔥

[@ArjunNarula1122]

Thanks Tanish!!

[@raeleenkanda8270]

Great project ✨👏🏻

[@ArjunNarula1122]

Thank you Raeleen!!🌟

[@ritikgupta8478]

Great project !!

[@ArjunNarula1122]

Thank you Ritik!!!

[@mehakjain1956]

Great project!!✨

[@ArjunNarula1122]

Thanks Mehak!!✨

[@vimminarula5523]

Nice project God bless you

[@ArjunNarula1122]

Thank you 😊😊

[@varunbansal2633]

Great 🔥🔥🔥

[@ArjunNarula1122]

Thanks 😊

[@designerguy_13anuragsharma59]

Good going folks

[@ArjunNarula1122]

Thank you sir!

[@diwanshi6669]

Well done👌

[@ArjunNarula1122]

Thanks 😊

[@mehakgoyal7173]

Well explained

[@ArjunNarula1122]

Thanks Mehak!!

[@harshitsingh480]

have you done rtl synthesis and rtl to gds flow of it?

[@debasishkar761]

IN the GITHUB code I am seeing this signal is not driven "mask_enable" but used as a load.

[@runcongkuang7965]

Thanks for your wonderful explanation. However, I can't find the logic of mask_enable in the code. Do you miss that?

[@mahendrabirla5337]

Very Nice explanation can you please say where did you defined burst time and time quantum

[@anweshangoswami5636]

Thank'a a lot for this Arjun..keep up the good work. Can you please let me about resources where I can read about the architecture of this whole design in depth..that will help for a better understanding. I searched in google, but only the scheduling algorithms are there..there isn't anything about the architecture & working anywhere!!

[@SaharshAggarwal]

Where did you drive mask_enable?

[@user-fc8iu9zn4t]

from where does mask enable value come ?

[@rinagharat29]

Hey... can you please make video on round robin arbiter using xilinx vivado

[@tanujicr]

the code is missing mask_enable logic, when do you set it?

[@JinWonLee]

Where is the FSM code for the mask_enable signal? Is your code compilable?

[@chbhaskar6413]

Did u get the answer

[@JinWonLee]

@@chbhaskar6413 No......

[@chbhaskar6413]

@@JinWonLee i too have the same issue

[@Weekend_vloger_yt]

🔥🔥🔥🔥🔥🔥🔥🔥

[@ArjunNarula1122]

😇😇

[@user-jt9uq6re3e]

Can you implement this on FPGA?

[@harmanchawla33]

👍👍

[@user-jt9uq6re3e]

In testbench code it is not working for other inputs other than you have given can you please tell me that how to clear that

[@ankur6098]

did you implement the state machine..?

[@user-jt9uq6re3e]

@@ankur6098 how to implement that ??? Please tell me

[@chaitanyagupta6668]

nice

[@ArjunNarula1122]

Thanks!!

[@gokulp6878]

great.can you explain i2c verilog fsm ?

[@ArjunNarula1122]

Sure Gokul, Stay tuned for more projects. I2C is definitely on the list.

[@gokulp6878]

@@ArjunNarula1122 thank you

[@satishpampanaboina2409]

Sir design of QSD Multipller Using HDL. Is my project please give me vedeo link.

[@ArjunNarula1122]

QSD multiplier is definitely on the list. Till then stay tuned!!!

[@satishpampanaboina2409]

@@ArjunNarula1122 Sir i have interview so please send me QSD multiplier using HDL video link

[@battlizer1101]

Noice

[@ArjunNarula1122]

Thanks!!

[@somilkumar4163]

where is the code

[@ArjunNarula1122]

Verilog Code - github.com/Arjun-Narula/Round-Robin-Arbiter Do consider Subscribing to the channel for more such videos.

[@rohandutta5694]

Good explanation but little confused on how the code works. I didn’t understand what is the driver for mask_enable. There is some part of the logic missing for that signal

[@ArjunNarula1122]

mask_enable in code is the output signal from the LASMAS state machine (refer to 7:10 in video), which gets connected to CE (Enable pin) of register. Whenever CE is active, the outputs from encoder logic gets stored in the register. To complete the data-flow modelling for the general topology such that it justifies the circuit , it was included in code for better understanding. You can consider it as the value in ‘lgnt’ (from encoder logic) non-blockingly gets stored in lmask0 and lmask1 variables depending upon reset conditions.