Verilog, FPGA, Serial Com: Overview + Example

[@GroupRoblox]

Bless you. I have lab for FPGAs but most of the time I’m doing the work myself since the TA does not know what is happening and just references the solutions. I was trying to implement this myself but for dear life could not get the timing right, which made the characters on my 16x2 LCD appear wonky. Thank you!!!

[@x87-64]

Hopefully you continue this wonderful series.

[@shivanshtyagi7222]

Dear professor, thank you for this incredible video, just what I need to pass my Comp Arch exam in 7 hours.

[@hhp3]

Best of luck!

[@netanelyakobov6196]

Thanks, Professor, very helpful!

[@notebook2866]

legend is back

[@techfriday2227]

thank you for sharing your knowledge

[@PulpFreePress]

Wonderful presentation! Thank you!

[@saifayman3984]

gem just one of youtube's gems

[@michaczerwonka8720]

when do you build the riscv CPU on the FPGA ?

[@fonecelautorizadatim882]

Obrigado. Os conceitos e fundamentos explicados nesse video facilita o entendimento sobre FPGA.

[@rubenrojobaez4890]

Excelente explicacion. Muy buen video.

[@ksco3309]

Thanks, Professor Harry, this is very informative, will there be more videos like this?

[@hhp3]

See my videos at Blitz64.org/EveCore

[@ilanmer1234]

Thank you very much proffesor! Could you please tell us what book are you using?

[@lizhougao5037]

great video! Thanks!

[@gauravshahi2308]

why have you taken clocks_per_bit as 543 in main module, what is the calulation of it?

[@quant-prep2843]

where is the code in github ?

[@muhammadmahsheedali4436]

Just different names

[@karthigaasenthilkumar6267]

Thanks a lotttt sirrr!!

[@ksco3309]

WOW

[@dark.violin]

awesome

[@thanatosor]

This guy hand writing is easier to read than text editor font 😂

[@cisspyoussef8566]

Hi how can I contact u