VHDL Design and simulation of 4:1 mux(multiplexer) using VHDL XLINX(Pune university)

[@arpitanweshsahoo8718]

Sir showing type void doesn't match with string literal in error box.... please tell me how can I fix it 😢

[@soumojitghatak8804]

brother why not use bus in the input of the mux?

[@JubeenTalukdar]

Can i add entity by myself like can i type entity and all by myself without adding

[@abhinaythodupunuri277]

Thank you very much very clear explanation

[@warsnewz4094]

Sir kindly reply me if I want to to verilog code then how will go? With connected fpga module

[@pedrovieira4806]

thanks for your help

[@rohanpurkaith155]

good work Abhishek

[@abhishek9721452503]

thxx bhai

[@sathishgolukonda6451]

You're super bro👍👍👍👍👍👍👍❤️❤️❤️❤️❤️❤️❤️

[@abhinaythodupunuri277]

Can u please tell how to do demx in same way

[@dipankarbagade7933]

Hello sir can you give me the video for VHDL 32:1 MUX SIMULATION

[@abhijeetparge3565]

TBT not running dude plz soln this

[@aniketbhoite7168]

Just remove the clock lines n u will good to go

[@aniketbhoite7168]

Just remove the clock lines n u will good to go

[@bhushanbarde5041]

Thanks bro👌

[@gabrielcardenas3337]

Vengo del 1NV21😎👍🏿

[@hajarevaibhavraj8123]

👍🏻👍🏻👍🏻

[@abhishek9721452503]

Hajare Vaibhavraj thx bhau

[@watchingowl1984]

nice video...

[@abhishek9721452503]

watching owl thx

[@Noname-lz5jf]

Tq

[@ravikiran9089]

can i have your mail id