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Learn how to use a procedure in VHDL to create cascade counters in a clock module.
The blog post for this video:
vhdlwhiz.com/u...
Procedures are a type of subprogram in VHDL that can be used instead of copy-pasting code. They are like mini-modules which can be invoked from a line of code within a clocked or concurrent process.
Unlike a function, which is the other type of subprogram in VHDL, a procedure doesn’t have a return value. Values can be returned from procedures through the parameter list though. The parameters can have any of the directions “in”, “out”, or “inout”, just like in a module can. The inputs may be signals, variable, or constants.
Another thing that separates procedures from modules is that procedures can contain wait-statements, while functions cannot. They can consume time. Because of this, procedures are often used in testbenches as bus-functional models (BFMs).
Procedures can be declared in the declarative region of the VHDL file, or the declarative region of a process, or they can be declared in a package.
*** Update:
The IncrementWrap procedure contains a bug that causes it to fail in newer versions of Questa/ModelSim that follow the VHDL standard more closely.
The Wrapped signal should be cleared outside of the If statement. See the updated version of the procedure in my blog post: vhdlwhiz.com/u...