⨘ } VLSI } 11 } Clock Domain Crossing (CDC) } Multi Voltage Domains } LEPROF }

Multi-voltage domain crossings. Modern integrated circuits are no longer simple circuits running on one or two static voltage domains but having dynamically switched multi voltage domains. Signals pass through these voltage domains. There can exists crossings between different clock domains having same voltage domain or different clock domains and different voltage domains or same clock domains but different voltage domains. This becomes quite important to pay attention to these crossings otherwise these crossing may screw things up in your chip. If signals cross voltage domains (DVFS techniques to reduce chip power), signals receiving flops may suffer metastability. This is same problem as CDC.
This lecture discusses design techniques for voltage domain crossings, clock domain verification under multi voltage scaling. Typically UPF (unified power format) based CDC flow is used to properly verify along with manual checks such kind of design issues. Typical techniques for multi-VDD designs use level shifters, multiplexers controlled by power control logic, and or retention cells.
If you need consultation on clock domain crossing verification, you may contact for for cdc workshop and training. We would be happy to help you.
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1LEPROF / LEPROF / LEPROFESSEUR

[@aakashgupta7332]

I quite didn't understand the issue with the second example. Why would the circuit at time t=11:00 in the video, have a metastability issue? If we are finally adding a sync cell in the destination domain, wouldn't that be sufficient to solve the CDC issue here?

[@Leprofesseur]

It is a recommended practice to have stable signal cross clock boundaries, if signal (input to sync cell) toggles it affects the MTBF and further reliability concerns that depends on toggle frequency. Second sync cell for iso_en improves signal stability and improves reliability, however if iso_en signals is stable then second sync cell is not needed.

[@ayushsrivastava7527]

The synchronizer u have put in Voltage Domain V1, shouldn't it be synchronized with respect to Power CLK instead of V2 clk ?

[@Leprofesseur]

NO.

[@ahmedemara9707]

if the PMU clock is coming from the same source as the V1 domain for example, should i consider PMU & V1 domains as synchronous or asynchronous?

[@Leprofesseur]

Can you elaborate more?