⨘ } VLSI } 27 } Coding techniques - a simple fifo design in verilog } LEPROFESSEUR
57:49
⨘ } VLSI } 27 } Coding techniques - a simple fifo design in verilog } LEPROFESSEUR
2 жыл бұрын
⨘ } VLSI } 26 } CDC, Reconvergence } LEPROFESSEUR }
13:30
⨘ } VLSI } 26 } CDC, Reconvergence } LEPROFESSEUR }
2 жыл бұрын
⨘ } VLSI } 24 } Reset Domain Crossings, Solutions } LE PROFOFESSEUR }
9:53
⨘ } VLSI } 24 } Reset Domain Crossings, Solutions } LE PROFOFESSEUR }
2 жыл бұрын
⨘ } VLSI } System Verilog Assertions } LE PROF }
17:12
⨘ } VLSI } System Verilog Assertions } LE PROF }
3 жыл бұрын
⨘ } VLSI } 23 } Transmission Gate Logic Circuits } LE PROFESSEUR }
29:04
⨘ } VLSI } 23 } Transmission Gate Logic Circuits } LE PROFESSEUR }
3 жыл бұрын
⨘ } VLSI } 22 } Pass-Transistor Logic Circuits } LE PROF }
28:01
⨘ } VLSI } 22 } Pass-Transistor Logic Circuits } LE PROF }
3 жыл бұрын
⨘ } Complex Concepts Made Easy } LEPROFESSEUR }
0:20
⨘ } Complex Concepts Made Easy } LEPROFESSEUR }
3 жыл бұрын
⨘ } Complex Concepts Made Easy } LeProfesseur} Learn with HR
0:15
⨘ } Complex Concepts Made Easy } LeProfesseur} Learn with HR
3 жыл бұрын
⨘ } Multi-criteria Decision Making, Analytical Hierarchy Process (AHP) } LE PROFESSEUR }
47:41
⨘ } Multi-criteria Decision Making, Analytical Hierarchy Process (AHP) } LE PROFESSEUR }
3 жыл бұрын
⨘ } VLSI } 21 } CMOS circuits design, physical layout, combinatorial logic, PUN, PDN } LEPROF }
26:27
⨘ } VLSI } 21 } CMOS circuits design, physical layout, combinatorial logic, PUN, PDN } LEPROF }
3 жыл бұрын
⨘ } VLSI } 20 } CMOS Interconnects } LEPROF }
32:32
⨘ } VLSI } 20 } CMOS Interconnects } LEPROF }
4 жыл бұрын
⨘ } Tips for choosing a university for higher education } LEPROFESSEUR
53:22
⨘ } Tips for choosing a university for higher education } LEPROFESSEUR
5 жыл бұрын
⨘ } VLSI } 19 } System Verilog } Assertions } Protocol Verification } LEPROF }
24:28
⨘ } VLSI } 19 } System Verilog } Assertions } Protocol Verification } LEPROF }
5 жыл бұрын
⨘ } VLSI } 18 } Clock Domain Crossing } Questa CDC / Mentor / 0-in } LEPROF }
33:27
⨘ } VLSI } 18 } Clock Domain Crossing } Questa CDC / Mentor / 0-in } LEPROF }
6 жыл бұрын
⨘ } VLSI } 17 } Power dissipation in electronic circuits } ASIC Power Analysis } LEPROF }
40:04
⨘ } VLSI } 17 } Power dissipation in electronic circuits } ASIC Power Analysis } LEPROF }
6 жыл бұрын
⨘ } Le Professeur - Learn with HR
0:19
⨘ } Le Professeur - Learn with HR
6 жыл бұрын
⨘ } VLSI } 16 } Verilog, VHDL, Do You Write a Good RTL Code } LEPROFESSEUR
25:52
⨘ } VLSI } 16 } Verilog, VHDL, Do You Write a Good RTL Code } LEPROFESSEUR
6 жыл бұрын
⨘ } VLSI } 15 } Static Timing Analysis (STA), concepts, paths, and how to fix violations } LE PROF }
51:16
⨘ } VLSI } 15 } Static Timing Analysis (STA), concepts, paths, and how to fix violations } LE PROF }
7 жыл бұрын
⨘ } LEPROFESSEUR }
0:12
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7 жыл бұрын
⨘ } VLSI } 14 } Latch-up & CMOS Technologies } LEPROF }
23:11
⨘ } VLSI } 14 } Latch-up & CMOS Technologies } LEPROF }
7 жыл бұрын
⨘ } VLSI } 13 } Floor-planning & placement tips } LEPROF }
26:24
⨘ } VLSI } 13 } Floor-planning & placement tips } LEPROF }
7 жыл бұрын
⨘ } VLSI } 12 } Metastability in digital circuits } LEPROF }
31:29
⨘ } VLSI } 12 } Metastability in digital circuits } LEPROF }
7 жыл бұрын
⨘ } Economics } 12 } Economic Growth, GDP, Business Cycles } LEPROF }
18:29
⨘ } Economics } 12 } Economic Growth, GDP, Business Cycles } LEPROF }
8 жыл бұрын
⨘ } VLSI } 11 } Clock Domain Crossing (CDC) } Multi Voltage Domains } LEPROF }
14:11
⨘ } VLSI } 11 } Clock Domain Crossing (CDC) } Multi Voltage Domains } LEPROF }
8 жыл бұрын
⨘ } Algorithms } 45 } Ant Colony Optimization } Mathematical Formulations } LE PROF }
17:21
⨘ } Algorithms } 45 } Ant Colony Optimization } Mathematical Formulations } LE PROF }
8 жыл бұрын
⨘ } VLSI } 10 } Clock Domain Crossing (CDC) } Reset Domain Crossing (RDC) } LEPROF }
14:45
⨘ } VLSI } 10 } Clock Domain Crossing (CDC) } Reset Domain Crossing (RDC) } LEPROF }
8 жыл бұрын
⨘ } VLSI } 9 } Clock Domain Crossing (CDC) } FIFO } LE PROF }
19:42
⨘ } VLSI } 9 } Clock Domain Crossing (CDC) } FIFO } LE PROF }
8 жыл бұрын
⨘ } Algorithms } 44 } Ant Colony Optimization } part - 1 } LEPROF }
16:10
⨘ } Algorithms } 44 } Ant Colony Optimization } part - 1 } LEPROF }
8 жыл бұрын
⨘ } Matlab / Octave basic concepts } LEPROF }
47:09
⨘ } Matlab / Octave basic concepts } LEPROF }
8 жыл бұрын
Пікірлер
@adrienthiers470
@adrienthiers470 2 ай бұрын
keep making your video that's really helpfull when "discovering" CDC
@sharonbeaulah9210
@sharonbeaulah9210 5 ай бұрын
I have a doubt. Let's say two signals are coming from two different clock domains to a single destination clock to be used in a combinational logic. How to solve the convergence in that case?
@Leprofesseur
@Leprofesseur 3 ай бұрын
you may need to have some logic in Tx domain, e.g. combine both signals in Tx, flop resultant signal in Tx domain and then pass to Rx domain, synchronize it and use in Rx domain.
@pd128
@pd128 7 ай бұрын
At time 6:49. can we write it this way? assert property (@(posedge clk_m) $stable(data) [*NUM_CYCLES] |-> req); In a way, read it like, expect req to be asserted if the data is stable for 3-cycles. Whats the best practice?
@Leprofesseur
@Leprofesseur 6 ай бұрын
you could have variable number of cycles, probably randomized number between min and max based on architectural guidance.
@RandomHubbb
@RandomHubbb 8 ай бұрын
When you say SYN, does it have 2 flops in it? Or is it a single flop? :)
@Leprofesseur
@Leprofesseur 7 ай бұрын
It depends on technology, for simplicity let's assume 2/3 flops, however different technology nodes have specialized sync cells designed for metastability which are supposed to be hand instantiated in the design. For example, intel 10 nm requires 3 meta sync flops if clock frequency is more than 950 MHz.
@sekaransekaran9487
@sekaransekaran9487 10 ай бұрын
Thanks for the great information Could you please share details why Async reset de-assertion should be synchronised with clock
@Leprofesseur
@Leprofesseur 7 ай бұрын
if asynchronous, it will lead to unstable state in flops. It is required to have all flops in known state after de-assertion of reset.
@AnuragYadav-lb5gy
@AnuragYadav-lb5gy Жыл бұрын
Sir Your Voice is breaking.
@Leprofesseur
@Leprofesseur 7 ай бұрын
Sorry for that
@luisabbott2469
@luisabbott2469 Жыл бұрын
"Promo sm" 🙏
@rrangana11
@rrangana11 Жыл бұрын
In my excel calculation I get the Case1 MTBF correctly BUT by just changing the f_clk frequency I am not getting your MTBF numbers. I am getting 23.36128 Hrs only
@Leprofesseur
@Leprofesseur Жыл бұрын
Thank you for message, I will need to check on this.
@rohitkankal3857
@rohitkankal3857 Жыл бұрын
There is only 21 seconds of video sir...
@Leprofesseur
@Leprofesseur Жыл бұрын
Thank you for message, I was trying to create shorts, it seems youtube does not put it in shorts. Please check other videos on CDC issues where I explained in detail with potential solutions to deal with the situation.
@prabhakarvadakattu534
@prabhakarvadakattu534 Жыл бұрын
Great teacher
@Leprofesseur
@Leprofesseur 7 ай бұрын
Thank you!
@gyaneshjha5167
@gyaneshjha5167 Жыл бұрын
I think there still.lies the problem of reconnvergence glitch at the end we are using a combinational logic on the signal crossing the clock domain which is not correct we must always sync the signal first before using it. The ideal solution would have been to push the entire combo logic in the dest domain use a synchr. first then use combo logic afterwards. Am i missing something here
@Leprofesseur
@Leprofesseur Жыл бұрын
my understanding is that push the combo logic in Tx domain, pass one wire to destination Rx domain, sync it before using via appropriate synchronizers from library. if you have multiple signals then it becomes more complex. Manny a times a global synch mechanism is used in combinations with local mechanisms of dealing with this situations.
@ariklapid7
@ariklapid7 Жыл бұрын
5:48 Thanks for the video! Something doesn’t make sense here; We close timing between the metaflops and the capture FF. There shouldn’t be any glitch there. What can happen is a phenomenon called synchronization ambiguity. Propagation delay towards the D of the metaflop may vary between the two, so that one net is synchronized in delay. It is not a glitch issue. Meaning, we don’t know when the Q of the launch FF will arrive at the D input of each synchronizer; It may be launched and arrived an epsilon before SETUP (then it will take 1 cycle to synchronize), an epsilon after HOLD (then it will take 3 cycles to synchronize) or it may stabilize sometime before the posedge of the sampling clock, and then it will take the most common, 2 cycle-synchronization. But, even if both metaflops synchronize the signal within 2 cycles, nobody promises both will start synchronizing at the same time, because these are async paths
@Leprofesseur
@Leprofesseur 7 ай бұрын
thanks for detailed comments, typically in cdc paths timing is not closed by primetime or similar static timing analysis tools, it is considered false paths. Logic designers need to ensure correct mechanism for CDC. CDC tools (mentor's 0-in, now Siemens) are used to do CDC analysis and help to find out where in full chip CDC paths are, tools can dump out assertions which are then simulated to ensure that data los can be captured and addressed before design can be signed off. Microarchitecture and logic design need to ensure correctness that design. Every chip has standard procedures to handle on-chip clock and reset domain crossings. I hope this clarifies.
@尚大华
@尚大华 Жыл бұрын
Thanks a lot
@Kannadainfohub18
@Kannadainfohub18 Жыл бұрын
Could you please let me know the syntax to include waiver in waiver tcl file
@Leprofesseur
@Leprofesseur Жыл бұрын
depends on which tool are you using. synopsys vc uses little different than mentor/0-in. check at tool user guide for corresponding tool. it is not that difficult, e.g. -waive -from <path> -to <path>. You can also use GUI to apply.
@Kannadainfohub18
@Kannadainfohub18 Жыл бұрын
@@Leprofesseur I'm using questa lint and questa cdc tool from mentor, and I got syntax by using gui thanks
@m101ist
@m101ist Жыл бұрын
Should have a thin layer insulation Soi² split between down of the bulk.
@HDgaming345
@HDgaming345 Жыл бұрын
Amazing! Could you please also make a video on clock tree synthesis to add to your already excellent VLSI lecture series?
@Leprofesseur
@Leprofesseur 7 ай бұрын
Thanks for feedback.
@HDgaming345
@HDgaming345 Жыл бұрын
Good video sir. Can you please explain in a little more detail what you mean by "PHY"? Also, the latch in analog domain, is it a digital latch like a D latch?
@Leprofesseur
@Leprofesseur Жыл бұрын
PHY - physical layers, mixed-signal designs. e.g. MIPI, USB, SERDES etc. latch/flops standard digital design cells.
@HDgaming345
@HDgaming345 Жыл бұрын
@@Leprofesseur thanks 👍🏼
@API38
@API38 Жыл бұрын
Thank you so much!
@edwinargueta4330
@edwinargueta4330 2 жыл бұрын
This is a god send!!🙏 Great video!!
@Leprofesseur
@Leprofesseur 2 жыл бұрын
Thank you 🙌
@tvscharankruthik7661
@tvscharankruthik7661 2 жыл бұрын
Video is interesting and helpful. I have a doubt. in the end, how are we solving the glitch issue? Is the solution, shown in the end a complete solution to CDC reconvergence? The glitch causes wrong value to be sampled by the 2- FF sync. right? Please clarify
@Leprofesseur
@Leprofesseur 2 жыл бұрын
first sync flop latches the async value, waits for whole cycle before it passes the value to 2nd sync flop, in theory it should be good enough for 2 stage flops but sometimes 3 stages are also used, depends on various technology factors and clock frequency. These are specially designed flops to deal with metastability. however in designs other qualifier signals are typically used which act as enables with few cycle delays with some handshake/ack mechanism between sender and receiver, designers need to think about both data loss of signal in receiver domain and accuracy of signal. it is good idea to have handshake mechanism when clocks are not source synchronous. In high speed designs typically clocks frequencies and ratios are known and often source synchronous, there open loop cdc solution is also good, however designer need to make sure to have enough pulse width of sampled in receive domain to be properly sampled synchronously in receive clock domain.
@albanec4702
@albanec4702 2 жыл бұрын
Thank you a lot: this is the only place I`d found a detail explanation of how vEB tree realy looks like(~45 min) 👍
@Leprofesseur
@Leprofesseur 2 жыл бұрын
Glad it was helpful!
@simpleChatGPT
@simpleChatGPT 2 жыл бұрын
Very clear explanation. Can you please do a small example of a problem with sub-criteria? Thank you
@parag5644
@parag5644 2 жыл бұрын
Explained very Simply and in the best way... Thanks a lot, Sirji..
@Leprofesseur
@Leprofesseur 2 жыл бұрын
Thanks!
@ayeshanaikodi6764
@ayeshanaikodi6764 2 жыл бұрын
Um, collinear lines don't intersect \_(0.0)_/. That's the opposite definition of collinear lines.. They're collinear if they have an angle of 0 or 180 degrees between them. Someone please correct me if I'm wrong. Trying to find a good video to understand this concept and everyone's saying different things -.-
@Leprofesseur
@Leprofesseur 2 жыл бұрын
it may help: mathworld.wolfram.com/Collinear.html
@kickerbud
@kickerbud 2 жыл бұрын
This is one of the most coherent, concise and informative lectures I have seen. Very very well done. Thank you! 🙏🏽
@Leprofesseur
@Leprofesseur 2 жыл бұрын
Glad it was helpful!
@nishanthkanala
@nishanthkanala 2 жыл бұрын
The example of Bin2Gray needs more clarification. If we are converting the enable and read signals to gray, why is it ensured that only one signal is changing? It is true only when we are counting up in a sequence right? Am I misinterpreting this?
@Leprofesseur
@Leprofesseur 2 жыл бұрын
basic idea is to have only one signal out of vector pass the clock domains. grey code ensures that one signal is changing at a time. if more than one signals are changing, they will reach to destination domain at different times, that may lead to wrong values in logic in destination and will mess up things. Gray code need to be carefully used as well, it will need to circle the full length of the counter, e.f. 3 bits will have 8 values.
@abdulazeezshaik1378
@abdulazeezshaik1378 2 жыл бұрын
Thanks alot sir. Today i came to know about your channel. I wonder how did i missed this great learning platform. Thanks for your efforts sir. Love from INdia :)
@Leprofesseur
@Leprofesseur 2 жыл бұрын
Welcome!
@lirarahman7988
@lirarahman7988 2 жыл бұрын
This informational video is fantastic. He has explained thoroughly. Loved his comparison with junk and healthy food. Much needed for my class. Keep it up.
@Leprofesseur
@Leprofesseur 2 жыл бұрын
Thank you! for compliments. Are there any other topics of interests your students may like?
@amirghorban2044
@amirghorban2044 2 жыл бұрын
nice
@Leprofesseur
@Leprofesseur 2 жыл бұрын
Thanks
@muhammadasyrofialkindy8066
@muhammadasyrofialkindy8066 2 жыл бұрын
Thank you sir, you explain clear and concise
@Leprofesseur
@Leprofesseur 2 жыл бұрын
Glad it was helpful!
@andrewlee8653
@andrewlee8653 2 жыл бұрын
Thank you for sharing!
@Leprofesseur
@Leprofesseur 2 жыл бұрын
No worries!
@MrNewAmerican
@MrNewAmerican 3 жыл бұрын
Clear, cogent and incredibly concise. The hallmark of a great teacher.
@Leprofesseur
@Leprofesseur 3 жыл бұрын
Thank you!
@rbouraoui
@rbouraoui 3 жыл бұрын
Great job. Remember only one signal has to be changed moving from one clock domain to another! I love it. Thanks a lot!
@Leprofesseur
@Leprofesseur 2 жыл бұрын
You're welcome!
@ketangupta1910
@ketangupta1910 3 жыл бұрын
Corman Question!!!:)
@amanshaikh3645
@amanshaikh3645 3 жыл бұрын
Thank you
@Leprofesseur
@Leprofesseur 2 жыл бұрын
You're welcome
@tatianakulikovatatiana3790
@tatianakulikovatatiana3790 3 жыл бұрын
Thank you so much for this video!
@Leprofesseur
@Leprofesseur 2 жыл бұрын
You are so welcome!
@ankushchavhan1054
@ankushchavhan1054 3 жыл бұрын
Thank you for the great explanation. RDC can cause big problems which are very difficult to catch in conventional verification and testing methods. They are also very hard to debug. There is very less material available to learn RDC Analysis. Could you please take a through 0-in RDC analysis flow and also share material to learn more about this topic. Thanks again.
@Leprofesseur
@Leprofesseur 2 жыл бұрын
Thank you for feedback. I have created another short video for explaining RDC problem and solution which may be helpful: kzbin.info/www/bejne/n3K4dJuliN6bjrc
@FalseZer0
@FalseZer0 3 жыл бұрын
great explanation, thanks
@Leprofesseur
@Leprofesseur 2 жыл бұрын
Glad it was helpful!
@tejaskoshatwar3428
@tejaskoshatwar3428 3 жыл бұрын
Descent explaination.....Keep it up...!....Thanks you...
@Leprofesseur
@Leprofesseur 2 жыл бұрын
You are welcome
@shaktishrey7216
@shaktishrey7216 3 жыл бұрын
Thanks for the explanations!
@Leprofesseur
@Leprofesseur 2 жыл бұрын
Glad it was helpful!
@aradhanakumari4029
@aradhanakumari4029 3 жыл бұрын
Very nicely explained. Thank you so much for your efforts
@Leprofesseur
@Leprofesseur 2 жыл бұрын
Thanks!
@shanusingh3814
@shanusingh3814 3 жыл бұрын
Great lec
@shanusingh3814
@shanusingh3814 3 жыл бұрын
Nice lecture plz make few more lecture on assertion by the way it is more informative . Thanks 🙏
@saiyaman7296
@saiyaman7296 3 жыл бұрын
Assersens*
@Leprofesseur
@Leprofesseur 2 жыл бұрын
Sure 👍
@RasheedPattan
@RasheedPattan 3 жыл бұрын
Hello, and thank you for the excellent explanation. I'm curious as to why you chose number six while selecting attributes. Even numbers, according to Prof. Sati, are for intermediate importance, although I believe you prefer 6 times rank. If I'm mistaken, please correct me.
@Leprofesseur
@Leprofesseur 3 жыл бұрын
Thank you for message, I am not sure I understood your question, there are 7 criteria and 4 alternatives in the example explained. There may be some differences from the Prof. Satti's paper which is ok. You may follow Prof. Satti's original work as well.
@Naruto_Uzumaki313
@Naruto_Uzumaki313 2 жыл бұрын
@@Leprofesseur HI, when we have negative values in the alternatives, should we use the same logic in terms of beneficial and non-beneficial normalization.
@Leprofesseur
@Leprofesseur 2 жыл бұрын
Take a difference, normalized values, could you elaborate more on how you are doing comparisons/calculation that you are getting negative values.
@truptichauhan3634
@truptichauhan3634 3 жыл бұрын
very informative and clear explanation. Thanks for sharing.
@Leprofesseur
@Leprofesseur 2 жыл бұрын
Glad it was helpful!
@ahmedemara9707
@ahmedemara9707 3 жыл бұрын
if the PMU clock is coming from the same source as the V1 domain for example, should i consider PMU & V1 domains as synchronous or asynchronous?
@Leprofesseur
@Leprofesseur 3 жыл бұрын
Can you elaborate more?
@raghvendragiri1523
@raghvendragiri1523 3 жыл бұрын
Professor, you are awesome. The way you explain the concepts is excellent. Thanks to youtube they recommended your channel.
@Leprofesseur
@Leprofesseur 3 жыл бұрын
Awesome, thank you!
@kruparaja4892
@kruparaja4892 3 жыл бұрын
Very helpful video...Thank you so much
@Leprofesseur
@Leprofesseur 3 жыл бұрын
Glad it was helpful!
@jrmartinez6396
@jrmartinez6396 3 жыл бұрын
Thank you for your time. This was very easy to follow and understand.
@Leprofesseur
@Leprofesseur 3 жыл бұрын
Great to hear!
@GSKHappyLearning
@GSKHappyLearning 3 жыл бұрын
does it end over here...?
@Leprofesseur
@Leprofesseur 3 жыл бұрын
not sure what you mean?