CLOCK TREE SYNTHESIS (CTS) | INNOVUS | ENCOUNTER | PHYSICAL DESIGN | ASIC | ELECTRONICS | VLSIFaB

[@alphabeta8298]

Best video for CTS.. expecting more such kind of video..

[@VLSIFaB]

thanks

[@amitthakur7983]

Nice video sir..i have never seen with that details..keep it up

[@runupathak6865]

Nice video 👌 10/10

[@srinukatari9939]

Very good video for Learners

[@VLSIFaB]

thanks ..kindly check for other videos also..

[@VLSIFaB]

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[@pranotisalankar7418]

Hi VlSIFAB team. Thank you for your effort. These are very useful videos. Could you please explain how to fix setup and hold violations ? Thank you

[@VLSIFaB]

Check the playlist.. already videos on setup and hold present

[@VLSIFaB]

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[@StayInBliss]

grt work sir

[@thesigmacorporates08]

Nyc video

[@VLSIFaB]

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[@krishna420hrushi]

Hi sir ,next post CTS optimization video ..i m not able to find

[@gopik4686]

Nice video

[@VLSIFaB]

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[@dipankarsaha702]

Thank you very much Sir....I came to know so many things like what are the inputs are needed for CTS,what are the contents of spec file etc....please discuss when we do skew grouping,how to balance the skew ...I mean what tool does internally to solve the issues in CTS....

[@VLSIFaB]

Dipankar Saha sure..will discuss this things

[@VLSIFaB]

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[@vbr87]

please explain why do we need to generate the clcok spec file before staring the cts, and how it is different than sdc file why can't we use sdc file directly instead of spec file?

[@VLSIFaB]

yes we need to generate the file (in case you dont have the constraints with you) in spec file we give constraints specific to cts stage so you can think it as an sdc only but with some additional info like ndr, crosstalk..

[@VLSIFaB]

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[@sairam9738]

Hi VlsiFab team....very clearly explained... can you guys make a video on Post CTS optimisation and its techniques in detail ?

[@VLSIFaB]

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[@vedavyas8496]

ur videos are good. when willl u post clock tree optimization? can u make it fast. thanku for informational stuff

[@VLSIFaB]

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[@vizier_of_the_dead]

Do you have a full playlist of all the videos related to PnR? This is very helpful

[@VLSIFaB]

No...but It's been divided in floorplan placement CTS Routing. Routing yet to come..others are in the playlist itself.

[@VLSIFaB]

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[@tuhindas9487]

VLSI fab thank you so much, can you tell me after desining a layout in cadence Innovus, how can I calculate/get at what frequency my ASIC will work?

[@fixeco4013]

Tuhin Das the frequency depends on what you designed ，if it meet your request，it is the frequency

[@rkmag1141]

One way is to check sign off worst negative slack.

[@VLSIFaB]

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[@tejaswinik836]

can you pls explain how to solve drc's, and how to do power planning

[@VLSIFaB]

Sure .stay tuned to 5 minute series, will upload it for sure shortly.

[@VLSIFaB]

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[@nishangkhamar4540]

can you please share link for post CTS optimization and cts balancing ?

[@VLSIFaB]

will be uploading next week.

[@VLSIFaB]

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[@krishna420hrushi]

Can u share this 2nd video sir

[@komatisurendra4751]

Hii sir my insertion delay is -1.556 this value after post CTS is completed but how to reduce these value in post CTS

[@VLSIFaB]

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[@FerozAhmed_PhysicalDesign]

the video content and explanation is good but please upload in order, if you are explaining CTS then CTO should be next but all the parts of all stages are missing this makes all videos incomplete.. its a suggestion, your work is amazing just complete what is expected next without jumping to next stage.

[@VLSIFaB]

Thanks feroz.. definitely i hv understand u r point..but till now i was making videos on ppl demand.. anyways I hv series of playlist..you can check it in the playlist section..i am working and making some more fruitful videos for the beginner's

[@VLSIFaB]

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[@felipeferreira1960]

Hello, how are you? Can anyone tell me how I can specify the constraint for a pin of the "inout" type? Should I specify as input and output individually? Thanks

[@VLSIFaB]

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[@user-yh7tt4pf6x]

How to restore the design init.enc?