What You Need to Know When Routing DDR3 Part 2 of 2

[@hansonquan1140]

This is truly helpful, especially since I'm using Altium. Thank you for posting it.

[@NineDotConnects]

Thank you for your kind words! We are glad that you found our video helpful.

[@johnfoster7374]

So the part with short long short long I have always started at the source and pretended I am driving a car. If I don't make the same number of right turns as left turns then I know I have a problem. Just found the videos today and am really enjoying them

[@keremoktem899]

Thank you very much for this detailed video on DDRs. I have question: for the Address/Command/Control (ACC) signals, it looks like from the routing @46:00, they use all the layers for routing. Can we do the routing of ACC signals using many layers? I try routing ACC on 1 layer, it is impossible, on 2 layers it is very hard to do the serpentines.

[@NineDotConnects]

Because the timing of the ACC signals is not as tight as those of the data bus signals, it is okay to route the ACC signals on different layers and have (possibly) different propagation delays, as long as the overall timing requirements are met. And as you found out, it is difficult, if not impossible, to get the length matching of so many signals on just one or two layers.

[@keremoktem899]

Thank you very much for your reply. I am relieved to hear that. Based on the video you posted and the feedback from you, I shall try routing them.

[@NineDotConnects]

Glad to hear. Good luck!

[@shankarnarayan488]

Thanks for the excellent video. Really helped to understand deeply.

[@NineDotConnects]

Great to hear!

[@jackphilpott3178]

Thanks for the helpful video. Are there any length matching requirement between the byte lanes and addr/cmd/ctrl signals?

[@NineDotConnects]

Length matching is only required within an individual byte lane, including the DQS clock. The ACC signals only have to be matched to the CLK signal. There is no matching that is needed between the byte lane groups and the ACC groups, other than meeting the overall timing requirements based on the clock speed and cycle timing.

[@Parvi_]

Thanks for uploading.

[@ibobaba06]

How can we achive the pin lentgh numbers, are they in the datasheets ?

[@NineDotConnects]

I believe you are asking about the pin delay. That is a value created by the FPGA software. This delay will vary based on the device's configuration, so it will have to be generated once the FPGA pins have been assigned. For Xilinx, it is called Vivaldo.

[@ibobaba06]

@@NineDotConnects do we need to match the pin delays for IMX6 or whatever non FPGA SoC devices ?

[@NineDotConnects]

Yes, you do.