When Four Become One: Intel's Next Xeon is BIG

[@WesFelter]

I was going to complain about ignoring leaks but you won me back with "horse-based binding agent"! 😂

[@unitedfools3493]

"Leaks".

[@rhekman]

Undomesticated equines could not remove me from watching Ian's video.

[@AlmightyGTR]

Worked with 8 socket system only once in my life. For a healthcare org which had extremely large Caché DBs with data for ~10 million patients. It ended up working well, but required quite a lot of initial heavy lifting to tune it for memory access bottlenecks while operating under a single kernel. Good times.

[@wpyoga]

10 million patients seem like a small number, why does it need so many cores? (I assume multicore CPU's on each socket)

[@AlmightyGTR]

@@wpyoga 10 million patients. Not 10 million records. Think about lab tests, reports, X-rays, medications, vaccinations, surgeries, treatment plans, etc. A single patient may easily 1000-10000 records associated with them, depending on age and ailments. Now if you go into the older age brackets records per patient number would only go up. It was the largest patient DB ever deployed by EPIC systems in the world. The project to deploy this MIS system was $1.4b in total costs.

[@wpyoga]

@@AlmightyGTR Yes, but it's not every patient that has 1000+ records right? I'm just confused as to why the database would be so big.

[@AlmightyGTR]

@@wpyoga seems like you have never worked in healthcare systems. All good. You know what you know.

[@onGlobalproductions]

Its hard to tune, some times I just give up, and use a dual socket system. Have multiple quad socket systems, 2 systems with 8 sockets (only one of them is x86) One system with 12 sockets (yeah sparc)

[@Veptis]

I loved the little ballet their marketing video did. It combines different dies, tags some above - embeds some below - cold welds others. Flips them for power via..... The coming generations will be even crazier. Don't know if it's my end - but the audio and video seem to be a few frames our of sync where it looks wrong.

[@hariranormal5584]

maybe your using pulseaudio

[@crayzeape2230]

Potato Sync TM

[@eclipsegst9419]

Everyone remembers Intel calling Zen "glued together chips" but who else remembers AMD calling the Q6600 "not a real quad core" for the same reasons?

[@technewseveryweek8332]

Most people don't remember the second

[@christophermullins7163]

Q6600 is a real quad core 😆 and that cpu is not a mcm hah

[@eclipsegst9419]

@@christophermullins7163 i mean, it doesn't have a separate IO die but it is two separate dies with 2 cores each. Same goal- More cores with less binning, even if it meant some latency penalty.

[@cavegoblin101]

Not only do I remember, I frequently remind people of those events.

[@thegeforce6625]

I'm using its Xeon derivitive right now, a 3ghz 8 core Mac Pro 2,1. I like to think of it as a quad socket, dual core system squished into the design and footprint of a dual socket, quad core system.

[@dewaynethomas3122]

I never went to college for computer science or anyhting, and this is really cool that you explain how cpu's work in a more in deptch way. Greatly appreciate it. Thanks.

[@Psychx_]

Hold on, 6-wide decode?! I thought this was insanely difficult or space/energy inefficient on X86 due to variable instruction lengths and one of the main advantages of ARM (it got fixed lengths) in terms of being able to easily squeeze more IPC out of it on a generational basis. Comparing Golden Cove or its successors with future Apple silicon will be very exciting.

[@TechTechPotato]

We keep asking Intel about it, they don't want to just yet

[@squelchedotter]

As Jim Keller said in the interview with Ian (after leaving Intel), you can just use predictors to predict the instruction length. So in the end it doesn't matter that much. (In general, modern high performance CPUs are so complex that the ISA doesn't really matter as it's such of a small part of the chip)

[@kamenriderblade2099]

x86 Assembly µOP has 6 pieces and is limited to 15 Bytes in size. So having a 6-wide decoder makes alot of sense since it covers all possibilities. Each µOP can have: - Prefix - Opcode - Mod-Reg R/M - Scale-Index-Base (SIB) - Displacement - Immediate So being able to process all 6 pieces would be incredibly helpful compared to only processing 4 pieces at a time.

[@mduckernz]

IIRC Zen 3 also decodes 6 instructions per cycle (I think this is the same thing, just stated differently?) And yeah it must be crazy complicated to do this!

[@Harish2923]

@@mduckernz no, they are different things

[@xBlizzDevious]

Surely if they're using tiles, their "glue" would be grout?

[@BarryTheCougar]

10:39 I didn't know there was a Q5 2022. You must be using some new quantum calendar 😂

[@justinharris5955]

Sounds like 2022 is going to be a long ass year 🤣🤣🤣

[@r3ddr4gon80]

Didn't you hear, the are inserting leap quarters now to combat the time dilation caused by the corona crisis :)

[@JigilJigil]

You should do a video about Tesla Dojo: their chip, module and supercomputer.

[@TechTechPotato]

It's on the list. 👍

[@JigilJigil]

@@TechTechPotato Great to hear that, thanks. 🙂👍

[@treyquattro]

good suggestion! Probably turns out it's a RISC-V implementation....

[@suntzu1409]

@@treyquattro is it really a RISC-V version?

[@treyquattro]

@@suntzu1409 I don't believe so! I think it's a proprietary design, but there's not much info on it (some people think it's mostly vaporware)

[@porina_pew]

If SPR is truly monolithic-like in internal connectivity it should be really fun to play with. One thing I've not liked about AMD's approach is the choke point that Infinity Fabric is between CCX, which I think plays a part in their decision to explore massive caches to mitigate against that.

[@johndoh5182]

Since releasing Zen 3: For server this is probably more of an issue, but that's going to vary greatly depending on the task. Well, it would also affect TR in the same way. If threads have to be passing data back and forth between cores on different die, it becomes an issue. Not much, but yes it can be an issue. For servers that are constantly serving data for different queries, this is going to be a non-issue. For video rendering or tasks that do something very similar, where in the case of video rendering segments can be handled by individual cores and then passes the completed segment to a main thread that's assembling a completed stream, then that's constantly using the interconnect between the chiplets. So, workload dependent. However, considering AMD's IPC is better than Intel's right now it doesn't seem like this interconnect has too big of an affect. For mainstream desktop the CCX is only a thing for 2 chiplet CPUs, since there's no longer a 4 core division. One could think that because there's still an IO die that this introduces latency, but an area where latency shows itself is in gaming, and right now Zen 3 in desktop is the best gaming product and very low latency. Part of this is because you're really only using one chiplet for gaming, but the other part is the core chiplet deals with part of the interface without the IO die from my understanding, based on the last time I looked at a diagram for Zen3. I could be wrong. Once you go over 8 cores then you start to get into workload dependent issues with having to pass data across the interconnect for cores on different die. The scheduler in the OS is supposed to keep threads created by the same application within a single chiplet, from my understanding. I suspect that Zen4 is going to be a total remake of the interconnect. AMD is scraping GloFo, and is using TSMC technology through and through, and I highly doubt one interconnect is going to be superior to the other when talking about AMD or Intel at that point. This is also technology that both AMD and TSMC have been working on too.

[@erbenton07]

Hey Ian, could you do a few videos with focus on the desktop. What does pcie5 and ddr5 mean for desktop performance? How soon will we see video and other cards with pcie5 support? does ddr5 really make a difference? What desktop processors can we look forward to? etc etc.

[@Speak_Out_and_Remove_All_Doubt]

Isn't it the interposers that make HBM really expensive? So if Intel is sprinkling interposers like it's confetti then won't these chips be ultra expensive to manufacture? And massively disproportionately expensive compared to a 96-128 core Zen 4 chip?

[@ladislavdobrovsky8826]

probably

[@CGIEBERT]

It's Intels highest price line I know: if it offers good performance per space and power cloud providers will pay nearly any price.

[@fat_pigeon]

Perhaps. But I know Intel has been investing heavily in packaging tech so they might have a competitive advantage there. Plus they could get economies of scale when they start interposing interposers in everything. He also mentioned (around 1:30) that EMIB requires much less silicon than a traditional interposer. So it may not be as expensive as it seems. P.S. Great username.

[@Speak_Out_and_Remove_All_Doubt]

@@CGIEBERT I just find it very unlikely it will offer better performance per socket per watt than a 96-128 core 5nm Zen 4 CPU but time will tell I guess. I think it will start to get very interesting when Intel starts using TSMC's 3nm node for their chips, seemingly before AMD has 3nm chips too.

[@Speak_Out_and_Remove_All_Doubt]

@@fat_pigeon let's hope so because if they can integrate HBM at a reasonable cost then we might start to see it trickle down to high end APUs. I still believe an ultimate all round chip (great for gaming and professional workloads) would be: 16 core Zen 4 80 EU RDNA 3 64GB HBM3 unified memory I'd pay $2k for that chip if the heat could be controlled so that the clocks are still decent but all of the above are meant to bring huge strides in energy efficiency. Plus the energy saved and the performance gained from having everything on the same chip/socket would be massive. When you break it down $2k isn't a bad price, $3k starts to get a little expensive but when you hear MS is only paying a little over $100 for the XSX APU then clearly AMD / Intel could make some serious profit from releasing consumer segment ultra high-end APUs.

[@steffeneilers8530]

Do you know when back in the v3 days, the 18-core processor had a wider package in the middle but was socket compatible with the other SKUs? Maybe they're doing a similar thing for SPR HBM

[@simplemechanics246]

10:45 Q5 WOW

[@PssupplementreviewsbyPete]

"First they ignore you, then they laugh at you, then they try to fight you and then they glue things together just like you" -Lisa Sun Tzu

[@Ligby]

4 Years after laughing at their tech, they finally managed to copy it

[@alexmarin7897]

Intel has been developing EMIB for advanced 2.5D MCM integration since 2008 and have used it in other products like FPGAs in 2015 before AMD used their own rudimental 2.5D approach for their own chips in 2017. And as explained in this very video Intel’s tile approach is nothing like AMD’s chiplet approach. The similarities end in that they are both using multiple dies and that’s about it. Also if it is the idea of MCM (multi-chip modules) we are talking about then AMD can certainly not claim that Intel copied them. Intel has done MCM chip designs since the 1990s well before AMD ever even thought to do. In fact, what you said in your comment applies to AMD as they were the ones that mocked Intel back in the Core 2 Quad days saying that Intel’s chip is not a true quad core but 2 dies glued together and claimed that theirs was superior because it was monolithic. it seems that AMD fanboys have short memory when it comes to their beloved AMD...

[@donpalmera]

@@alexmarin7897 Stop it with the facts. AMD is the plucky underdog so they can do no wrong, Intel are the incumbent so everything they do is wrong and someone else did it first, better and with moar nanometers and gigaflops. ARM is great because of it's risk instructions and X86 takes no risk so it's bad... and so on and so on.

[@mduckernz]

@@alexmarin7897 I think people are just salty about it considering Intel made fun of the approach, despite having done something much like it before as you said (although once AMD's IO die approach came in in subsequent generations with Zen 2 and later, this was no longer the case; Intel had nothing like that - only something like Zen 1 with multiple identical dies) - and then sought to follow the same path later on. It kinda feels like "sour grapes" / hypocrisy But yes the amount of personal investment in it is definitely concerning. Such is the way of things with brand attachment 🙄

[@alexmarin7897]

@@mduckernz -- Intel did not make fun of the approach. It was not even something that was said in public. This whole thing was from a power point presentation made under closed doors of which someone took a picture of and leaked to the press. In that presentation all Intel did was to point out the differences and benefits of their own monolithic design over AMD's MCM design. It was all a justification about the cost differences and not about making fun of. Also Intel's extensive experience with MCM in the past allowed them to know better than anybody else the limitations of that approach. In fact there were several problems with first gen EPYC. As Intel said back then with regards to MCM, it all boils down to developing the packaging, interconnect, topology and strategy technology needed to overcome the limitations and produce something that would be virtually as good as monolithic. And lo and behold 4 years later they managed to achieve it.

[@effexon]

@11:21 this looks eerily vega/HBM dies... someone said cache is simple compared to dram tho... is it in this case?

[@eugkra33]

I'm curios how much an interposer costs. Is it really cost effective to add an interposer in a situation where you want to turn a 200mm² die into 2x 100mm² ones, for example? Maybe it's just easier, and cost effective to deal with the yield loss at a certain point.

[@maxhammick948]

Interposer is incredibly basic - you could probably make one on a 1 um process from 20 years ago; AMD is only claiming 9 um spacing for their silicon to silicon bumps. It's only wires so there's less to go wrong, and testing is cheaper and faster as it's just checking for continuity

[@eugkra33]

@@maxhammick948 So why does everyone make it sounds like it took a decade of development? It does seem like a super easy solution. Ian does mention heat expansion issues. I wonder if that has more to do with it, or something outside of actual production costs.

[@capability-snob]

The hard part is lining them up!

[@劉奕彤-q6g]

@@eugkra33 theory is theory. There are many testing to make it work in real life

[@susanparr1006]

What about the "cost of MB real estate", which will eat into space available for DIMMs and expansion slots, due to the larger die size.

[@mkhornetHD]

I really do wonder, if Intel is planning a split in their lineup after Sapphire rapids. For me it would make sense that if small cores from Alder Lake perform well, they would allow for a server grade CPU with small cores only (or possibly a mix). That if we get the "1600 mm2" chip, it could contain 4x the number of cores (be it without HT). This would make a lot of sense to combat the ARM style CPUs that start popping up in the enterprise market.

[@es-yy2cm]

It's called Sierra Forest

[@mkhornetHD]

@@es-yy2cm Aight, need to educate myself some more then, thanks for the name

[@domm6812]

Thank you Ian for explaining that all so thoroughly! Very interesting, and I'm keen to see how intel deals with the kind of scaling problem they have with their tiles on lower core counts too.

[@rSkipping]

Different versions of SPR I guess Intel can still make smaller tiles for lower end, from 15 cores to 11 cores (cut 1 row), 7 cores (cut 2 rows and 1xEMIB). I'm kinda confident with the 11 cores part, it feels really compacted and elegant, no dead space in the corners.

[@magottyk]

So the top right while directly connected to Top Left and Bottom Right, does not directly connect to the bottom left and each tile has this missing connection. You mention that "it's so low latency", but that infers some kind of switching through emib, a direct connection would be effectively no latency and seamless. Am I missing something with the grid not seeing EMIB as hops between tiles or even seeing EMIB at all and that's what's making it effectively monolithic in operation?

[@TechTechPotato]

With the mesh, not every CPU is directly connected - it's a grid of connections. By doing a direct cut horizontal and vertical and keeping that mesh, you keep the grid intact, and thus the only latency is between mesh stops, which is as it would work if it were monolithic

[@BeatsbyVegas]

Any idea of what a 1600mm^2 die would draw in terms of power?

[@WesFelter]

350-400W

[@BeatsbyVegas]

@@WesFelter I mean that might not even be too hard to cool considering how big the die is and being able to leverage that into a large cold plate for the cooler.

[@WesFelter]

@@BeatsbyVegas A100 is also 400W so it is definitely possible.

[@alihouadef5539]

I would imagine that the mask design was tricky (and expensive).

[@powertoker5000]

Add 75ms delay to video to fix sync Ty.

[@crayzeape2230]

Potato Sync TM

[@Speak_Out_and_Remove_All_Doubt]

If the HBM version of Sapphire Rapids isn't expected until Q5, is the move away from 14nm still on track for Q47?

[@kwinvdv]

I wonder if patents play a role in this as well. At least I assume that AMD has a patent on the chiplet based approach. So the extra cost of Intel's approach might outweigh the costs of having to pay for patents licences.

[@concinnus]

The basic idea of chiplets doesn't qualify as 'non-obvious': not a valid patent. The specific implementation with Infinity Fabric is surely patented (and perhaps the I/O die), but Intel could design an alternative. They just didn't like the latency cost.

[@animaze86]

Are these suitable for Workstation use? or more HPC/Datacentre/Supercomputer space?

[@mrrolandlawrence]

surprised they didnt add some more extensions while they were at it. i feel there are not enough...

[@raphofthehills4405]

"Q5 2022" at 10:45 😂

[@goodiezgrigis]

EMIB is saving some Watts while expanding connectivity, but where is the limit of W/mm2 of heat that needs to be removed from the package. Even 3D stacking AMD is doing has limitations and cores are not stacked only lower power logic.

[@wbwarren57]

Sounds like we may have competition again! Yay!

[@anonymoususer3561]

Is the audio delayed?

[@kingtilly]

Is the EMIB like teeny tiny breadboard?

[@SuperNimbus]

kzbin.info/www/bejne/o4O0d318or6Al80

[@SuperNimbus]

There is also Co-EMIB along with Foveros coming up which is more advanced stuff. kzbin.info/www/bejne/fGrWnKeXfZpjrpI

[@KeyserSoeze]

Why does the video lag 0.5 sec? Incredible disturbing ^_^

[@NotAMinifig]

wrt amd and potential milan-X: This is another part where amd has a leg up to intel, because apart from the apu's and the semicustom stuff, amd kinda only makes one processing chiplet. which means they can more dynamically scale between desktop and server. In the last news about it, it seemed that the 3d cache was at least coming to desktop (I think optimistically by the end of the year). which means that IF amd wants to do milan-X and those 3d-cache ryzen desktop cpus are already in production, it's basically just taking a spool of those chiplets from the ryzen assembly line and plugging it into the epyc line.

[@BlacKi-nd4uy]

12:51 the lane lenght between the dies, is a lot smaller. will it cost much more? true. but the amount of advantages is really big. latency. smaller package. bigger dies. intel had no other choice, thats what i think.

[@jamesdk5417]

Thanks very much for another great video. 👍🏻👍🏻

[@DileepB]

It would be incorrect to say that SPR does not support CXL.mem. They do not support Type 3 devices. Type 2 devices need CXL.mem and Intel does support Type 2. Unclear as to what is missing that precludes Type 3. Could it be that Type 2 devices do not need all capabilities of CXL.mem?

[@tringuyen7519]

10 EMIBs per sapphire rapid CPU? Price? Wouldn’t this increase Intel’s silicon cost per CPU?

[@TechTechPotato]

Yup

[@cj09beira]

at the same time those are likely made on a much older node, and they are quite small so they shouldn't be expensive

[@WesFelter]

@@cj09beira I wonder about the cost of aligning 14 dies though.

[@teemuvesala9575]

Since Intel manufactures their own CPUs by themselves, this isn't as much of a factor for them as it is for AMD that has to pay TSMC dearly for all the extra silicon they use from them.

[@PrivateSi]

I like intels approach to vertical layering and horizontal connectivity over AMD.. If I was Intel I'd be developing a CPU package that has a monolithic die and multiple simple, low, strong chiplet connections (gold bumps/pins that fit into/onto the chiplet). Chiplets secured by a tight fitting sheath and heat sink combination that slides over each extended end of the elongated PCB.. maybe 8 sockets of 16 by 32 connector grids each. This is for main memory and possibly co-processors.. Super-fast, high bandwidth, high capacity DRAM.. -- Intel should bring out DIMMS with combined flash and disk cache / main memory that can back itself up using just the power remaining in the system in the event of a power failure.. These replace SSDs in all home PCs, with a standard design for laptops and PCs.. Shake up the market, improves speed at at all levels.

[@giornikitop5373]

intel has realeased 512GB ram modules, they are hybrid optane, but they are only supported in specific server models and they need special software support for the apps to make effecient use. no, ssd's are not going to be replaced any time soon by these modules, because of first, the high cost and second, the storage usually needed is always an order of magnitude bigger than ram...

[@Maxkraft19]

I would guess Intel is going to have to have 2 lines of Xeons at some point. These older core designs and newer Big-Little+ designs. I would guess that Sapphire Rapids is one of the last Intel Xeons to have all the same cores.

[@bryce.ferenczi]

Hello from the future where this still isn't out lmao

[@__aceofspades]

Another very exciting upcoming launch for Intel. Seems like they are going to turn around their whole company in the time span of 6 months... (obviously years in progress, but major launches are happening all at once). Really excited to see how Sapphire Rapids performs, but even more excitied for 120(?) core Granite rapids up next.

[@BRUXXUS]

While I’m not a fan of how Intel handled their business for a long time, I do hope to see some innovation and progress from them soon. Things have been delayed so many times that I’ll believe it when it’s a real thing. They’re good at marketing and platitudes, but haven’t exactly delivered on them yet.

[@denvera1g1]

IS that Rick Astley's face swapped onto an XFiles poster?

[@TechTechPotato]

Nope, that's _the_ single of Never Gonna Give You Up

[@brianmccullough4578]

Every drug dealer knows, to make money you gotta bag em up really small(eg.wafers) and then you get the most profit, you don't sell big bags(or wafers) and make $!

[@KangoV]

With AMD Genoa hitting 92 cores and another (can't remember the code name) rumoured to be 128 cores. How will Intel combat this?

[@scarletspidernz]

with more little cores lol

[@KangoV]

@@scarletspidernz Lol, yeah. I'd love to see AMD do a big server chip with 32 cores and 2 * RDNA 2 MCMs on a single package, all connected by an interposer. Now that would be something.

[@jdogdarkness]

@TechTechPotato hey do u computer have a field you work in or studied? If so which one(s)? I'm curious how u know so much lol

[@Creabsley]

Um what?

[@t0scanelli]

The window design should also help with cooling.

[@Zarcondeegrissom]

I'll try to ask on the 3rd, that flip thing, doesn't quite sound correct to me, esp considering much older quad op-amps. yet cool info. cool vid as well. B) I can understand if it's more twisting of data wires to line things up between flipped sections of circuits, the grain thing, I have doubts.

[@paulfrancis8836]

what's a computer ?

[@HUBBABUBBADOOPYDOOP]

Great. Now this means all new MOBO, RAM, PCIe slots, coolers, larger PSU? What kind of Socket? I've always wondered- Everything else exponentially increased by x-factor, why have instruction sets been locked at 64bit? Never see 128, 256, 512, 768, 1024, 2048 instructions? What's next after 486? (X86) and why hasn't that architecture moved at all? Is 128 Express Lanes some physical limit, too?

[@Berengal]

Am I going crazy or is the audio ever so slightly out of sync?

[@GamerBoy705_yt]

It is

[@crayzeape2230]

Potato Sync TM

[@alfredzanini]

New caméra?

[@edwardecl]

Something tells me these CPUs will be tricky to make / expensive.

[@teemuvesala9575]

They are, but tile based design is also better because of lower latency.

[@thelunchbox420x]

Thanks Steve.

[@nicbll]

10 months and its still not out

[@Psychx_]

Hey Ian, I am really looking forward to your future content regarding, well everything, but especially when it comes to Xe Arc. I have a gut feeling that this architecture is quite similar to GCN (i.e. 4096 stream processors limit, compute focus, hw scheduler). Maybe Raja got one step closer to the ideal GPU he envisioned all these times? :P I do hope that some low level details that allow for some more comparison get leaked/released soon.

[@Harish2923]

Except, Xe HPG can scale higher than 4096 stream processor's.

[@nerdgeekdc]

Is anyone else getting audio sync issues?

[@crayzeape2230]

Potato Sync TM

[@robertpennington1492]

Can you please do a video on MST

[@liaminwales]

The magic AMD did was one die from top to bottom. -The home user you get the benefit of most the features of top end slicon like cache size. -AMD got the benefit of keeping it simple and having massive options in binning slicon and packaging. Intel's custom setup for each line is cool but must cost much more for production/packaging and failure/binning rates. But it may just be that the performance is so amazing it's worth it? At least they will learn a lot from it, develop new tools and the next step may be amazing. Just the idea of simple scaling and a single die is hard to shake. PS cant wait for some custom slicon packages AMD has done to leek out, relay hope they have made some cool crazy CPU's. edit - hope you do a short on the Broadwell CPU you just reviewed, may be a fun comparison when AMD get there one out. At the time I saw mention of it and a few story's that it was used for high frequency trading I think, been a long time.

[@teemuvesala9575]

Remember though, if Intel manages to just keep their manufacturing processes competitive with TSMC in the future, they have advantage because they use their own fabs. For them, using more silicon is considerably cheaper than for AMD which has to pay dearly for all the extra silicon they use from TSMC.

[@Groovewonder2]

I've now realized you sound like an adult Larsa from FFXII and I can't unhear it.

[@TechTechPotato]

I regret that I've not played far enough into FF12 to know who that is. But after watching some videos, eh, so he has a British accent?

[@Groovewonder2]

@@TechTechPotato i forgot to clarify that you sound like how I imagine Larsa as an adult would sound, but the thought popped into my head and now it's stuck. Just something about the way you spoke for a part of the video.

[@johndoh5182]

AMD already said they're shifting wafers from GPUs to produce more EPYC CPUs. That was a couple months ago? They said that would happen starting this fall. They didn't say anything about those CPUs including the extra cache, but that doesn't mean anything. What it does mean, based on what they said, is they can't make EPYC fast enough and are shifting wafers to more profitable products.

[@0b1ivion]

there's a spider underneath the tiles

[@maxhammick948]

I predict that EMIB is far more energy efficient on a per bit basis, but Intel is sending more data over it so it'll wash out

[@eugkra33]

Is there a reason why V-Cache needs to be on 7nm? Couldn't they just do the cache on 12nm?

[@TechTechPotato]

Density.

[@eugkra33]

@@TechTechPotato but they are only covering half the die, and filling out the sides with some kind of other Thermaltake conductive material in an extra step. I would have thought going 12nm and covering the whole die would have been cheaper.

[@magneticshrimp7429]

TLDR I guess; ignoring the (of course better) core internals, logically looks very similar to AMD Zen1/Naples, but with a much superior interconnect (the achilles' heel of Naples), more cores per tile, and less flexible vs re-usability across the stack.

[@Runefrag]

This is going to be compatibility & optimization hell for developers.

[@nukedathlonman]

Wow is the chip huge though. And the tech around it is very interesting - can't wait to see it in action. This should be nice. But will be be enough to trade blows with Epyc? I know Intel isn't gluing chips together. And I trust they have developed a good mortar to use when back buttering the tiles. ROFL! Sorry, I couldn't help it.

[@benjaminoechsli1941]

As someone who does plenty of tile laying, that's a great thing to call it. 😆

[@BRUXXUS]

Delicious CPU frosting!

[@KeinNiemand]

so 128 core when?

[@hukama6911]

thumbnail reminds me of a certain aussie electric engineer

[@TechTechPotato]

Ha! @eevblog would be proud

[@zactron1997]

Speculation: I think Intel knows tiles aren't a good solution and that chiplets are far more value-efficient, but they want to take advantage of their in-house manufacturing to basically force a status quo that only they could possibly maintain. If they can keep everyone designing software for monolithic (or monolithic-esque) CPUs, then chiplets will still have that heterogeneous latency potentially causing problems with software.

[@teemuvesala9575]

chiplets always have latency issues, this is just a reality. you can try to minimize that problem with proper software engineering, but it wont go away. intel's tile approach is superior to amd's chiplet design technologically. it has much lower latency which is actually important in data centers. chiplet approach is probably cheaper, but this is how its always been with amd and intel historically. intel's approach has been superior technology at higher cost, amd has usually competed with cost efficiency.

[@ShannonFrailey]

This will make Microsoft’s datacenter licensing department very happy.

[@kusumayogi7956]

Intel : threadrippers are ryzen glued together

[@arcadealchemist]

waiting for DOJO consumer chips

[@2020Tech4U]

Glue ppl glue, it's all the rage now. I think if I de-lid my CPU and change the AMD stock glue with Gorilla Glue I can get better core clocks and better efficiency all around, yea thats what I'm gonna do, I'll update the post with the results.. UPDATE: That was a bad idea why did you let me do it?? There's Silicone everywhere! Wheres my Tandy?

[@ianmoone8244]

I just saw 2 tons of glue there! O.o

[@KaosArbitrium]

IPC is expected to double every 4 or so years from here on out, on both Intel and AMD. Next five years are gonna be insane.

[@unitedfools3493]

Er ... is it though?

[@GamerBoy705_yt]

Doubt it

[@giornikitop5373]

highly doubt it, ipc is advancing ~15% on every generation. it's overall performance that goes higher (bigger caches, higher clocks etc)...

[@dishdoggiegaming7254]

Where do they put the rice? lol

[@wongkoewei9829]

I don't see the awesomeness because I'm already using MCM AMD CPU for sometime now

[@Bruuman]

I love this high-end tech... just can't justify spending money on it 😅

[@christophermullins7163]

I use these bleeding edge technology to decide how much my next gaming pc upgrade should cost. It looks like the next few generation of consumer chips will certainly be an upgrade from my i7 7700. Hahah

[@Nib_Nob-t7x]

wow its been "ears" in the making

[@UncleKennysPlace]

Remember when anything that said _Xeon_ was an advanced and fast chip?

[@Psychx_]

Does Intel's tile based approach utilizing EMIB come with additional advantages other than max. achievable MCM size compared to a regular interposer? I remember Intel shaming AMD for "glueing" together their CPUs and now they're doing the same lmao.

[@TechTechPotato]

Not really

[@deedoubs]

Ears in the Making.

[@air-iq]

Pretty sure AMD v-cache has been rumored to be N6 but yeah we shall see how things play out

[@Shadowauratechno]

Even if Intel's right about their emib solution being faster than AMD's chiplet web (i'm not super confident it will be), it seems like they'll be increasing a few more issues with power, heat, and especially cost. AMD's web scales really well to high core counts without increasing price a crazy amount. Intel's solution looks like it will be very expensive in comparison

[@cj09beira]

yes amd should be in a much better position if a "price war" happens

[@tonyburzio4107]

Speed isn't why Apple is smoking Intel, "hot" is the problem. Some PCs are so bad they have been labeled "gross polluters" and banned in several states. Of course, the fact that Intel's best needs water cooling in a desk tower, and Apple's better is a laptop, doesn't hurt...

[@郭家銘-z4c]

NOT ENOUGH to compete with granite rapids which is outsourced to TSMC

[@fat_pigeon]

We're going to build a Xeon on the border between monolithic and multi-chip. Nobody builds Xeons better than us, believe me, and we'll build them very inexpensively. We're gonna build a great, big, beautiful Xeon, and we'll make AMD pay for it. It's gonna be YUGE! AMD has a trump card, you say? (11:28)

[@willh8112]

Cut-n-Shut processor!

[@MoviePhoneGuy]

nomnomnom chips

[@stuartlunsford7556]

For Intel, it seems like they doubled down on a technique to be different from AMD, no IO die. For AMD, it seems like they've coasted for too long on the base Infinity Fabric design. I hope we see AMD at least double the physical channels for IF interconnect, because the frequency increase has been lacking. From Intel, EMIB has a HUGE potential, maybe we'll see that integrated with dedicated IO silicon soon.

[@lucasrem]

you don't have it ???

[@butterflyblueshorts]

Glue makes sense considering you can make glue from a potato!

[@SwordQuake2]

"horse-based binding agent"

[@TonciJukic]

Your videos lately have serious issues with sound latency.

[@TechTechPotato]

The KZbin app is having issues recently

[@TonciJukic]

@@TechTechPotato Audio is late for me only for those few of the last batch. It's fine locally before upload? Maybe YT messes up specific audio encoding only?

[@georhodiumgeo9827]

Asking for a friend, what should you do if you make fun of your competition for using chiplets then end up using chiplets after you get spanked? FYI I do not work at Intel marketing.

[@unfairleyc]

Could you say they are using.. super glue? /s

[@moriyokiri3229]

Does a picture count as a Rick Roll?