Why Phase Noise Contributors in a PLL?

[@erolnigdelioglu7195]

Hello. the vco settling time is an error. why is this problem happening? as a result of my research, it is written in many places that this will be by Loop Filter. how can I check if the loop filter is doing its job. Thanks your answer

[@circuitimage]

Hi Erol, nice to meet you and thank you for the good question. Yes, the loop response could be an issue for the stability since it's a feedback system. Ideally, it should be negative feedback (NFB) to keep stable, but if there's the time constant or BW in the bad design of the loop filter, then that stability issue occurs to PFB. I'll make another video to discuss the stability of the NFB, not causing the PFB.

[@wty1992]

Great video! Could you also give some guideline in how to find the phase noise contribution from the charge pump? Did you use PSS/Pnoise or transient noise?

[@circuitimage]

Hi wty1992, nice to meet you, and thank you for asking. For the charge pump, you can use the PSS/Pnoise to save the simulation time since it's a periodic operation. Also, you can get the phase noise contribution from the PSS/Pnoise analysis easily.

[@wty1992]

@@circuitimage But I have a concern, in steady state, PLL should be locked. In this case, isn't PFD output supposed to be zero and thus charge-pump noise be zero (because both up&dn current source are off)?

[@circuitimage]

​@@wty1992 Hi wty1992, very good question. If the output pulse of the PFD is zero, the PLL would be in an open loop, wouldn't it? I assume not, therefore, the slight phase offset should still push the PFD/QPMP in a close loop to cover the whole PVT variation, not in an open loop. :)

[@kdh4301]

thank you 😊

[@circuitimage]

@KDH You're very welcome :)

[@kellyrolla]

Great video, thank you CC. By the way, could you please explain at 11:30, why the RMS Jitter was calculated by integrating from 10KHz but not from 0Hz? Thanks again

[@circuitimage]

Thanks for the good question. The 0Hz offset is just the carrier, which was not the phase noise. The 10KHz here is just a case study example. The minimum integrated frequency depends on your system usage. If your system is a serial link, and the BW of the RX CDR in the link is 1MHz, and you could even integrate starting 1MHz since the CDR would track any phase jitter below 1MHz, and you don't care. Does that make sense? Could you please let me know if my metal model image is still not clear to you? Thanks again.

[@kellyrolla]

@@circuitimage that makes sense. Thank you CC. Would you mind answer my question under the why discrete adaptation video too? Thank you again

[@circuitimage]

@@kellyrolla Thanks for the feedback. Also, I'm sorry for the oversight in that comment, and thanks for the reminder. I'll check it carefully :)

[@kellyrolla]

@@circuitimage thank you C C. Well explained. Is that possible for you to make a video on how jitter transfer in Pcie ( for example gen3) under different refclk architecture? Thank you again

[@circuitimage]

Hi Merlin, thanks for your suggestions and sounds good idea to me. I will do that.

[@user-qg8cz1rg1l]

good video，however the sounds is not large enough

[@circuitimage]

Hi Yujian, nice to meet you. Thank you so much for the good catch & feedback. I'll try to improve my recording sounds next time. I apologize for this inconvenience. 😅

[@user-qg8cz1rg1l]

another question，why integrate to nyquist frequency，i remember in a video before ,it is a value of pll output frequncy divided by 1667?

[@circuitimage]

Hi Yujian, thank you so much for the good question. The "DR/1667" was the low frequency of the integrated BW since the CDR should design for a BW > "DR/1667." But, the Nyquist frequency was the high frequency of the integrated BW since the signaling folding, and you only need to integrate to the Nyquist frequency without counting the noise aliasing. :)

[@user-qg8cz1rg1l]

@@circuitimage thanks for reply,i think i get clerified now

[@circuitimage]

😄 thank you so much for let me know. I am so happy that is clear to you right now.☺️