嗨！doctor您好，請問一般在業界設計serdes時，都是使用keysight ads還是cadense virtuoso居多呢？ 他們各自的優缺點又在哪裡呢？感謝doctor!!

This is just an amazing video. I'm a consistent consumer of your content. However I'd suggest you to add english subtitles since I sometimes find it difficult to follow your audio.

Hi CC, why does the reference you shared additionally uses a 1tap DFE when 14tap FFE is used? Is the FFE not sufficient for equalisation?

Love this one. Thanks CC.

Thank you for a high quality video

Thanks for your great video! At time 4:36, what does PMA in red mean?

The much awaited :D Thank you !

謝謝！

Hi , Thanks for the Video , i have doubts regarding the floating node from a long time .Glad that those doubts got resolved from this video 😊.Can you suggest any good book to explore these concepts much more? Regarding Reliability issues?

Interesting topic!! Considerting the original reason from NRZ to PAM4, there might be opportunity to apply analog type in some low loss channel. But with high loss channel, does it still work in analog solution?

Nice video CC, good to see Marvell's ISSCC paper reference for ADC based receiver. Cheers!

Very good informative video. This gives a top-level picture . Can you also share your knowledge from Specs to design perspective. Looking at the Specs how to decide various critical parameters for different sub-blocks.

謝謝！

Thanks 😊👍🙏💯

講完深奧的PLL，突然變成基礎數位邏輯了XD

I have been looking for a way to help my colleagues understand FFE/DFE and how they operate. Your tutorials are excellent, clear with very helpful visuals and examples of real device issues. Thank you for this entire series, sir.

Very useful content. Much appreciated by someone who has experience in the industry.

Thank you so much for your videos, they help me a lot. Could you please make video about sampler dead zone (strong-arm based sense amp dead zone), and how it affects jitter budget? I think it's related to setup and hold time of sense amp.

but what is the equation for current for supply independent biasing ? how to set the current ?

Can you share the slides to your lectures please?

Thank you CC. These information are really useful

Nice explanation. Can you please tell any text book ? we can refer regarding high speed SERDES blocks

A question on tx jitter is that , when using scope to measure jitter, there are options of constant freq, 1st order cdr, 2nd order cdr, so for protocol defined tx jitter, should we use constant freq or cdr? Since latter will filter out low freq jitter. So from jitter budget point of view, which method is correct?

Great explanation. Can you please make video on pre cursor isi and post cursor isi waveforms?

Hi: You can have a negative setup time in a FF, if a FF has a long clock buffer you will have negative setup time. Reason we don't see any negative setup time is because this clock buffer is only one

Thanks Chen for considering my request to make a video on Flops. Looking for Low power High speed flip flop videos in future.

Unable to understand anything...

Best explanation! What tools you guys use to draw the schematic and waveform? It's so good.

Thank you sir, that was to the point and summarized. Very helpful.

Dear CC, a) if we need CTLE stage & VGA stage , which one is 1st stage ? b) dLev is externally set voltage for signal swing? The voltage swing control (VGA) & CTLE peaking control tuning through out data transfer ?! It seems this dLev in the video NOT the same as so called dLev used for SSLMS taps (ISI cancellation), right? c) This VGA control , can we just use simple feedback (dLev in the video compare with input ) to tune ?

Hi CC, Thank you for such a great content. Its a gold mine and very upto date with industry rightnow. I am curious why don't people directly use DLL to generate 64 phases instead they go on putting PI after DLL. Is it due to accuracy? Also, CC if you can make a video on clock distribution techniques. That would be great.

Hello Dr. Chen. One Question about electircal idle. Why do TX need to apply complemental singal on the individual segments to generate idle? Since AC couple cap exists on signal path, no signal shall be received on RX if TX send the constant digital code as DC value is outputed. Thanks!!

Thank you great

Hello Chen quick question what about a push-pull current mode driver ? the transistors operates in triode region which is in contradiction with origiinal CM Driver (2T + 2R) we should as in VM driver to size the switches in the aim to ensure a good matching with RTerm. Could you carify this point please Thank you in advance !

thanks for this knowledge sharing. it looks like there is a typo in the hand calculation section. Gm unit is mA/V, but the formula is not like this.

this saved my ass

Hi Chen, Thank you so much for the very informative lecture. I have one question here: the Jitter bugget of TX is abbriviated as a total Jitter of around 30% UI. But the details of TX jitter is sometimes critical in certain applications. Could you please give some deepdive discussion on the TX Jitter? Thanks again!

Very useful and practical for design checking. Excellent 👍🤝👍

Excellent talk 👍

Thanks! It’s really helpful!

Thank you very much for sharing these valuable information. It is more helpful than basic design information. The PI circuit has two stacked devices in series with resistor. For high-speed design, such as 112GBPS PAM,4, what is the size of resistor, capacitor, I and power supply? Thx

Super video!

Super video.

You are the best.

I missed watching your videos for sometime CC, it’s good to revisit this concepts. I always had this picture of so called integrating PI in my head for high linearity PI. Thanks for sharing the video.

Good video. I think there is some error in the xor gate characteristics.

謝謝！

Thanks for the great content CC!

這麼優質的頻道！！ 我現在都推薦台大ICS做analog, PLL / SerDes 的學弟妹可先看這個當基礎！！