Why Voltage Mode Driver in a SerDes?

[@layt01]

Super video.

[@circuitimage]

Hi layt01, thank you for the kind words, and nice to meet you. :)

[@rangababuganta7725]

Thank you so much Chen.

[@circuitimage]

You're very welcome.

[@AkashGupta-po2bg]

Thank you so much Chen. I was waiting for this video. Could you please also explain the DAC based driver used in PAM-4 architecture?

[@circuitimage]

Thanks for the recommendation. I'll do what you suggested :)

[@circuitimage]

@Akash Gupta Here you go: kzbin.info/www/bejne/r33ReHljm9KklbM

[@po-yaohsu2052]

I have a question！ At 3:53, does the swing at VT (Rx) range from -0.5 Vdd to 0.5 Vdd？ So, the Vp-p equals to 1 Vdd？ Thx！

[@circuitimage]

Correct :)

[@circuit6874]

I'm designing the driver with Nmos-to-Nmos configuration in a single-ended setup. While it worked well with NRZ signaling, once I switched to PAM signaling, the performance degraded significantly, showing acceptable results up to -6dB when applying FFE, but not performing well beyond -10dB. Could you provide insights into the channel attenuation sensitivity differences between a Voltage-Mode Driver with Pmos and Nmos combination versus an LVSTL structure with Nmos-only transistors?

[@circuitimage]

Hi Circuit, Thank you so much for the feedback and good questions. 😄 The NRZ signaling matters but is not very stringent as the PAM4 (or higher levels) signaling; therefore, I'm not sure if the low swing VM (SST) w/ NMOS-to-NMOS configuration would be a good approach for PAM4 & high loss channel. On the other hand, the high swing VM (SST) w/ PMOS-to-NMOS configuration would provide a high swing, which may be better for PAM4 & high loss channels. Therefore, the Voltage-Mode Driver with PMOS & NMOS combination would have less channel attenuation sensitivity than the LVSTL structure. Thanks, CC

[@circuit6874]

@@circuitimage thankyou!

[@circuitimage]

You’re very welcome ☺️

[@user-kt5rx6hf9b]

Hi Dr. Chen, thanks for the great video sharing. I'd like to inquire a question to you. As your mention, we need to operate the current mode driver in saturation region and its behavior will like amplifier, so we can get bigger output swing by using current mode driver. And using the voltage mode driver in triode region can have a small voltage drop, so I'm wodering if we want to get bigger output swing and smaller supply voltage, we can combine the CM and VM, is it correct.

[@circuitimage]

Hi 育瑛, thank you for the great idea, which is very smart. Some people already implemented both combined the CM & VM modes driver as you mentioned, and I could present that idea some time later :) 😀

[@user-kt5rx6hf9b]

@@circuitimage Thanks for your reply, I see. Thanks again for the great video, it's really helpful😃

[@user-kt5rx6hf9b]

Hi Dr. Chen, I'd like to inquire one more question, if we want to use the function of Amplifier, the operation need to be at saturation region, but may I know why the output impedance(Z) will be infinity. Since the output impedance for OP Amplifier needs to be smaller as possible and input impedance needs to be bigger as possible, kindly please correct me if I'm wrong, thanks again.

[@circuitimage]

@@user-kt5rx6hf9b You're very welocme and I'm glad it helps. 😃

[@circuitimage]

@@user-kt5rx6hf9b Hi 育瑛, Thanks for the good question. You're correct, the OP Amplifier needs to be ~0 output impedance, but ~infinite input impedance. The amplifier here I referred to was the high-speed CML buffer, and the output impedance should be dominated by the impedance of the resistive load (RL) & the differential pair (RO), therefore, we'd like to have a maximum linear gain, we what the output impedance = (RL || RO) = (RL || infinite) = RL (very linear). Does that make sense? If not, please let me know and I could still not make it clear enough. 😄