Zynq Ultrascale+ Hardware Design (Schematic Overview) - Phil's Lab

Schematic walkthrough of an AMD/Xilinx Zynq Ultrascale+ development board hardware design, featuring DDR4 memory, Gigabit Ethernet, PCIe, DisplayPort, USB3 SS, and more! PCBWay www.pcbway.com
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[LINKS]
UG583: www.xilinx.com/content/dam/xi...
UG908: docs.xilinx.com/r/en-US/ug908...
UG1805: docs.xilinx.com/r/en-US/ug108...
ZU+ HW Design Guide: fidus.com/wp-content/uploads/...
Zynq Ultrascale+: www.xilinx.com/products/silic...
[TIMESTAMPS]
00:00 Introduction
00:41 Zynq Ultrascale+ Overview
03:39 Altium Designer Free Trial
04:15 PCBWay
04:59 System Overview
07:01 Design Guide Booklet
08:01 Ultrascale+ Schematic Symbol
10:50 Overview Page
12:14 Power
15:14 SoC Power
17:06 Processing System (PS) Config
18:46 Reference Designs
19:48 PS Pin-Out
21:32 DDR4
23:04 Gigabit Transceivers
25:22 SSD, USB3 SS, DisplayPort
27:26 Non-Volatile Memory
28:27 USB-to-JTAG/UART
29:20 Programmable Logic (PL)
30:09 Cameras, Gig Ethernet, USB, Codec
32:40 Outro

[@pietrogagliano4484]

You truly never fail to top yourself! Great work! My course board is about a week or 2 from being ordered as well. The course has really been a game changer in a lot of elements of my pcb design approach.

[@PhilsLab]

Thank you, Pietro - looking forward to seeing your design!

[@Seventhsu]

Hey Phil, big fan of your content so far. You mentioned the necessity of a heatsink for this chip; can we soon have a video on them? I would like to hear your take on things like heatsink material, mounting, grounding and RF decoupling for both chips that have metal pads exposed and chips that don't, and the use of intermediate materials like thermal paste or pads.

[@MegaTraxxas]

All these tutorials are so valuable, thank you

[@MikeHarris1984]

Wow, that lineup is awesome! I wish I went down the electrical engineering road when I got out of highschool and continued into that industry. I am doing it as a hobby now and love it. Same reason I love to program. I break up my programming into a all chunks and solve each part and move on to 5he next. It's like a little puzzle that I must figure out to get my program working. I find i do the same thing with my PCB projects and schematics layouts. In high school electronics Iearned basics, layout and building our own PCB with copper boards, masking and slushing in acid to etch the.board. Then TIN the paths and drill the TH components and then build. This is in the year 2000, so much has changed since then lol. Thank you again for the work you do on your videos. You have the BEST PCB design and videos out on KZbin that I can find. Now I'm a cyber security architect for a fortune 500 financial firm and 17 years into my career. Too old to jump to a new career. Lol. But hey, I can play for my hobbying

[@PhilsLab]

Thank you, Mike! Exactly, that's why I like it as well - loads of puzzles and problem-solving. Rather rewarding as well, seeing projects come to life! Cool that you've kept electronics as a hobby :)

[@DC-tq6nd]

This is awesome! I'm part of a student team currently developing DAQ for a prototype vehicle and we'll be making your videos mandatory viewing :)

[@PhilsLab]

That's awesome, thank you!

[@user-eh8rk4gw9p]

You always inspired us Phil! Danke!

[@PhilsLab]

Thank you!

[@VictorSoria]

Thanks a lot for all your hard work, Phil. This is hugely inspiring, even for people like me who are just starting out.

[@PhilsLab]

Thank you, Victor - I'm glad to hear that!

[@rolfdieterklein]

Excellent, thanks for the video, really great help for designs. Looking for the follow up.

[@PhilsLab]

Thanks a lot!

[@shakaibsafvi97]

Hi Phil, As always, amazing content. The Systems are getting complex. However, I'd like to see some use real world cases for this particular system. Cheers !

[@steffyabraham9497]

Thank you for the detailed videos. Your videos help me a lot in designing. Can you please list the regulators used in Zynq US power supply section?

[@keremoktem3832]

Hi, great video as usual. for the FTDI JTAG, it looks like in VCK190 there are some signals other than JTAG. Like ADBUS4 (VCCO_JTAG_ON) and ADBUS6 (FTDI_POR_B). Do you think these inputs should also be implemented on FTDI chip for JTAG connection?

[@tonydimichele4428]

Hey Phil, are you worried about cascading PG signals for your regulator enables not being controlled on the down sequence?

[@chruder83]

Nice project. Some note: In the "3_ZBU-PS-Config"-schematic, the JTAG buffer U300C (for TDO) should be placed in the other direction. TDO is in this case an input (JTAG data return).

[@PhilsLab]

Good catch, thank you!

[@x1000plusx]

Hey Phil, I wanna thank you for all your videos and inspiring me to my own project, a custom split keyboard using nrf52 soc with macros, rotary dial, thumb sticks with BT and usb capabilities

[@PhilsLab]

Hey, That's awesome - great project!

[@TrackballClick]

Does your network PHY supports hardware timestamping necessary for AVB or TSN? Or that support is replaceable by some development in PL? Definitively I would be interested in the courses related to this design, including PCB design and board bring-up.

[@dwagner6]

I would be very curious to hear about the process of sending parts to PCBway for assembly. I am sort of in this position at work (as an undergraduate!) where what we are trying to assemble is beyond our office’s capabilities, and we have all the parts on hand, purchased already. Thank you for all you do! I have learned so, so much the last couple years.

[@PhilsLab]

Thanks, Jack! I've only done that once before, but it was fairly straight-forward (except for customs, which delayed the process) - just ship to their address and declare contents as usual via a form. I'll see how it is this time with these rather expensive ICs..

[@sarbog1]

Very interesting. I just ordered the ADALM-Pluto... it has the Xilinx® Zynq®-7000 All Programmable SoC XC7Z010-1CLG225C4334... Should be fun to play with.

[@Jonathan-ru9zl]

Masterpiece

[@Blitzoschitzo]

Hey Phil, I'm starting to study electrical engineering in October but after my first 2 semesters I'll have to pick something to specialise in, since EE is such a broad subject. There are also 26 masters to choose from. May I ask what you Specialized in or what it was called? We have something similar to embedded engineering but we call it systems engineering

[@asidesigner8542]

You should add some high speed jsd208 ADC and DAC to the board too.

[@ryanmadden9276]

Hey Phil, great design and explanation as always. One thing I'd like to point out is the power supply scheme for the Codec on pg 18. I looked at the data sheet for the MAX9867 and only DVDDIO can support +3.3V, yet you have +3.3V supplied to all the VDD pins. The DVDD, AVDD, and PVDD pins require a +1.8V supply, with an abs max rating of +2V for each. I would urge you to change this to avoid a costly rework and destroyed codec. From one hardware designer to another. cheers

[@PhilsLab]

Thanks, Ryan - yes, you're right. I changed that after my schematic check a bit after making the video. As stated at the beginning, this was an initial/draft schematic.

[@ryanmadden9276]

@@PhilsLab Good catch! Keep up the great work - your videos have been essential references for my pub design projects!

[@lonelymechanic3688]

where do we learn the coding part?

[@TheExGuy_]

Been using the Xilinx kria kv260 which has the same SoC , but couldn’t think of any designs or projects to implement. Waiting for the course covering this SoC :). Suggestion: would you please consider doing y machine learning accelerator designs , thank you :) .

[@PhilsLab]

Yeah, I never had ideas for off-the-shelf devboards either.. Thanks for the suggestion, I'll look into that

[@--JYM-Rescuing-SS-Minnow]

U'r super helpful! love it!! had no idea pcbway sold dry lunch sacks!!

[@PhilsLab]

Thank you!

[@user-qf6yt3id3w]

You can see why people like PCIe, USB3 and DisplayPort. It's all serial so you don't need many traces and all can be done with the gigabit transceivers on an FPGA.

[@PhilsLab]

Exactly :)

[@dm3on]

Thank for such awesome video! How does shared memory works between FPGA and ARM CPU (via RAM I guess) ? I guess, what I am asking, for example; is there way to offload compute function to FPGA that would be called by linux kernel and exposed in user space ?

[@PhilsLab]

Yeah, you can do that. Simplest/most common I believe is to have an AXI bus/stream interface between PS and PL.

[@creativelectronics]

Sizin ürünleri çiftliklerde kullanıyor olabilirler çok iyi alternatif başarılar dilerim projelerinizi beğeniyorum Alitum güzel program.

[@Nbec95]

I'm designing my first PCB right now. Most of what I learned in the process I learned from you - so thanks so much for that! I've got at least one question, though. Based on your advise, I used net labels and net ties to give every pin on the pcb a meaningful name. Now I run into an issue where a) I've got no space for the net tie footprints on my pcb or b) they are so small, that I cant route a trace because of minimum track clearance between diffenrent nets. I just need to strap some neighbouring enable pins to VDD and would simply like to link them all up with a trace. Should I dont use net ties in that case? Btw I'm planning to submit my design for your reviews, when it's finished.

[@PhilsLab]

Thank you, I'm glad to hear that! Regarding net ties - I typically use 0R resistors instead. Otherwise, with net ties, I have them in the schematic until I've routed them, then remove them. For me, it's more of a 'reminder' when it comes to layout and routing.

[@tiborkiss3944]

I don't have now the time to fully verify that the MAC PHY does support hardware timestamping or not? I am thinking of AVB or TSN support.

[@MuhammadQasimRauf]

Thanks Phil for peek into your latest work. I sincerely hope Xilinx people won't come after you for sharing all this information with such vivid details, without a penny from us KZbin community. Quick question, is there a specific reason why you don't add component designators in your finished layout?

[@PhilsLab]

Thanks, Muhammad! Haha yeah I hope so as well.. I know some don't agree with this, but I don't see much particular reason to do so, given a well-done assembly drawing (especially in space-constrained designs). I've also confirmed this with the instructors from some IPC PCB design courses.

[@MuhammadQasimRauf]

@@PhilsLab I agree as well. I noticed you don't add designators, which obviously made me feel relieved as it was really a pain in the neck to place em underneath a BGA. Thanks for that.

[@asmi06]

Typically if the board is not meant to be assembled manually, you don't need designators. I assemble my FPGA/SoC boards manually, so I leave them in.

[@jatigre1]

So, let me see if I got this correct. You can technically built a Smart 4K TV or monitor with Display Port input for a fraction of the cost, with this setup, not to mention all the other cool stuff you can achieve with it?

[@spicypepper5391]

Do you have any recommendations for where to get started on these types of projects? I wanted to take a crack at doing an Intel Agilex 7 FPGA accelerator with CEM edge fingers for Gen 5 PCIE, but not sure how to go about it without an insane cost for the required low-loss stackup material.

[@PhilsLab]

I have a few FPGA-based hardware design videos covering simpler designs on the channel. Otherwise, I also have a full course that gives a much more thorough walkthrough (11.5hrs of content, link in the description).

[@Ziferten]

Hi Phil, careful shipping those MPSoCs to China. If you purchased from Mouser (a U.S. company), you may have unknowingly agreed to terms and conditions that preclude your shipping those to countries like China (ITAR). Not trying to discourage you, just make sure you do your due diligence before shipping them.

[@stevelee2504]

FYI. These starter kits are made in China. Careful not to ship it to USA 😂😂🎉🎉🎉

[@EngineerAnandu]

Link Not working: ZU+ HW Design Guide

[@m1geo]

Is your ATLAS board is open source? I'd be interested in looking at the design in detail.

[@PhilsLab]

I'm afraid not at the moment - sorry!

[@gsuberland]

Not sure if something changed in your audio setup recently, but might wanna dial up the sibilance filter a bit; the "s" sounds get quite harsh in this video.

[@PhilsLab]

Ah yeah, sorry about that - I forgot to add the de-esser in this time. Went a bit overboard with compression on the voice. Will be fixed next vid!

[@lucas_liano]

You are awesome

[@PhilsLab]

Thank you!

[@EngineerAnandu]

Please provide the excel sheet.

[@hanfman1951]

Why did you marked some components with a red cross?

[@PhilsLab]

Those are do not place (DNP) parts.

[@thekaduu]

Could have use MTG blocks and build you a space laser... Oh well :)

[@jhonchirstofer1895]

hello sir

[@Mtaalas]

I've never done FPGA stuff and i've been always wondering if you ahd to order a thousand, or then thousand units, would the price come down significantly or not... Because frankly, taping out an ASIC is very VERY expensive and I wonder at what price point / product volume that would even make sense. And FPGA's are popping up constantly in very high volume products (tens of thousands to hundreds of thousands of units) which makes me think tape out has gone even more expensive than before and FPGA's are getting more affordable... but 300€ for piece is quite something.... pushes any device you design around that to 1000€ or more almost regardless of anything...

[@deathblowhere]

Agreed. Those crazy prices are just artificially risen up by corporate greedy b*stards unfortunately.. Just take a look at any other descent FPGA chips - there are all around and above 100 USD mark per pop, even in volume..

[@tolkienfan1972]

"Missile and munitions"!?

[@sc0or]

Isn’t a simple ARM SoC for let’s say €40 + PCIe-to-FPGA + FPGA for €50 is worse than €400-4000 FPGA like this? How do they sell such ICs?!.. PCIe speed is enough to exchange data with an FPGA, that will perform expensive parallel tasks IMHO. It will remain actual a couple of times longer than it is calculated.

[@alocin110]

Instead of AMD use Intel. Thanks.