really good video, explained the theory and also how to approach the question well.

if we are considering the PS and NS as %d, then why have we taken reg[2:0] 3 bits to store the states?? can't we directly take reg PS,NS; in the code, just like we took in mealy fsm code?? Please help in clarifying my doubt

Sound is very low Sir otherwise explanation is good.

Gutka thook kare boliye sir

Why we are considering max for AT and min for RT they both are in Max cornor so we need to consider both max delays only i cant understand can in explain ?

yha pe aapne mealy ke logic ki tarah hi same block me direct state leke declare kyu nhi kar diya PS,Ns kyu liya ?

How are you able to get state in your waveform?

Thoda tej bolke video fir se bano yaar ....good work

module fsm_1010( input clk, input reset, input in, output reg out ); parameter s0=0,s1=1,s10=2,s101=3,s1010=4; reg [2:0]ps,ns; always @(posedge clk) begin if(reset == 1'b1) begin ps <= s0; out <= 1'b0; end else ps<=ns; end always @(ps,in) begin case(ps) s0 : begin ns <= in?s1:s0; out <= 1'b0; end s1 : begin ns <= in?s1:s10; out <= 1'b0; end s10 : begin ns <= in?s101:s0; out <= 1'b0; end s101 : begin ns <= in?s1:s1010; out <= in?0:1; end s1010 : begin ns <= in?s1:s0; out <= 1'b0; end endcase end endmodule . . . This code should be right for 1010 sequence otherwise I'm getting 10101 sequence.

the videos are so precise and so understandable. Thanks a lot

for s11, can you explain the (1/0) 8:04

Good Explaination HAre krishna tq prabhu

Only this video helps me

Onky video that helps me

For Hold Time Constraint @4:45 Contamination Delay used but @7:35 Propagation Delay ??

Bro taught verilog better than my prof and also under 20mins!! Great explanation!! Btw How are you running verilog in vscode?

brother ye vs code me setup kaise kiya verilog ko??

mealy machine keep getting toggled around s0 & s1 state, because you didn't introduce next state login in in the code.

sir why we are not using nonblocking statements

Good Keep it up man✨

maven silicon lol

informative video sir

Nice explanation sir

u clearified it so well but muh se guthka nikal k bolna hota h sir....very nicely u explained

excellent sir.help me a lot

thanks man.....this literally was the code which I was not able to make neither got on internet.....VERY VERY THANKS deep from my heart

Thank You So Much, Bro! Excellent explanation with the right example.🤗

Thank you so much sir, even my tutor couldn't explain this easy, bahot tuff padae, woh bache kuche bachon ko aaya samajmein

Hey instead of hardcoding the input how can we give user input at runtime

Voice is low

I am getting the output as '1' after one clock cycle on questa sim for the same. This is my output log: # 0 ps || in = x || out = x || PS = x -> NS =x # 5 ps || in = x || out = 0 || PS = 0 -> NS =X # 15 ps || in = 0 || out = 0 || PS = X -> NS =0 # 25 ps || in = 1 || out = 0 || PS = 0 -> NS =1 # 35 ps || in = 0 || out = 0 || PS = 1 -> NS =2 # 45 ps || in = 1 || out = 0 || PS = 2 -> NS =4 # 55 ps || in = 1 || out = 0 || PS = 4 -> NS =5 # 65 ps || in = 1 || out = 1 || PS = 5 -> NS =1 # 75 ps || in = 0 || out = 0 || PS = 1 -> NS =2 # 85 ps || in = 0 || out = 0 || PS = 2 -> NS =3 # 95 ps || in = 1 || out = 0 || PS = 3 -> NS =5 # 105 ps || in = 1 || out = 1 || PS = 5 -> NS =1 Why is this happening ? This is happening in other Moore implementations provided in other videos too.

Excellent. Tq.

Thank you

thanks for the video

brother, can you create an installation video of this ? like how to use verilog in VS Code

GG! For 1101, we are assuming we are reading from MSB to LSB

how we will do if starts with 0 , then their wiil we 2 S0

Thank you so much for this very useful & ur concepts is understanding

Bohot badhiya samjhaya bhaiyya🔥

bravo....the best🤩

sir audio thodi poor hai but teaching top class .

Keep it up 🙌🙌

Nice content... really informative 🙌🏻

thank you so much for sharing, what vs code extension do you use to view output waves?