Moore 1010 Sequence Detector Verilog Code with Testbench || Part 1 ||

[@sho-kun8939]

Thank you so much sir, even my tutor couldn't explain this easy, bahot tuff padae, woh bache kuche bachon ko aaya samajmein

[@Ichigo-c4y]

yha pe aapne mealy ke logic ki tarah hi same block me direct state leke declare kyu nhi kar diya PS,Ns kyu liya ?

[@shrutenradadiya4166]

module fsm_1010( input clk, input reset, input in, output reg out ); parameter s0=0,s1=1,s10=2,s101=3,s1010=4; reg [2:0]ps,ns; always @(posedge clk) begin if(reset == 1'b1) begin ps

[@manjunathmalagi791]

sir why we are not using nonblocking statements