FSM in One-Shot || Mealy, Moore, Overlapping, Non-Overlapping || Verilog + Testbench ||

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VLSI PP

VLSI PP

Жыл бұрын

Пікірлер: 9
@gabbarjadhav2293
@gabbarjadhav2293 Ай бұрын
Good Explaination HAre krishna tq prabhu
@harshalikapadnis603
@harshalikapadnis603 2 ай бұрын
Only this video helps me
@anupammathur17
@anupammathur17 Жыл бұрын
Bohot badhiya samjhaya bhaiyya🔥
@duelgodgaming5227
@duelgodgaming5227 2 ай бұрын
brother ye vs code me setup kaise kiya verilog ko??
@dharmeshubnare8166
@dharmeshubnare8166 Жыл бұрын
Nice content... really informative 🙌🏻
@tejabollam4606
@tejabollam4606 11 ай бұрын
Excellent. Tq.
@shubhamshaurya1281
@shubhamshaurya1281 Жыл бұрын
how we will do if starts with 0 , then their wiil we 2 S0
@vlsipp
@vlsipp Жыл бұрын
you can name ideal state as s1. for example you want for sequence 0110 then 1st state or ideal state will be s1 -> s0 -> s01 -> s011 (mealy) and s1 -> s0 -> s01 -> s011 -> s0110 (moore).
@ajithmanisaialigati4931
@ajithmanisaialigati4931 Жыл бұрын
bravo....the best🤩
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