Is this a question, or what? The project is documented in the linked report. The project is 8 years old. The ONLY documentation is the report.

I know nothing about the device. I do know that FPGAs are compute universal, so the answer has to be ‘yes’. It would probably mean changing most of the code.

did you read the linked report?

@@ece4760 yes

Our server will not serve python files. I changed the extension so it should work, by you will need to fix the file extension.

i don’t know.

did you read the linked report?

youwill have to write a state machine which generates VGA timing pulses.examle: people.ece.cornell.edu/land/courses/ece5760/DE2/indexVGA.html

@@ece4760 Thank you!

supporting code people.ece.cornell.edu/land/courses/ece5760/index.html#links

did you look at the lectures for this lab? Lab 4 at kzbin.info/aero/PLKcjQ_UFkrd43P4lgzCot1hgiUu8onfaj

also people.ece.cornell.edu/land/courses/ece4760/labs/f2021/lab3heilcopter/Lab3/Helicopter-PIC32.html

Possible? Yes. Easy? No. You will need to recode every detail.

since the project is 7 years old, the only documenttion is the report. Sorry. Do you have a specific piece that is missing? The course documentation from 7 years ago is still online.

@@ece4760 Sorry, I'm not sure about this, but all the data type is "unknown" or "high impedance" after running the simulation.

@@宋姿儀-o8w there is not nearly enough info here for me to understand what yu are actually doing.

@@ece4760 I would like to ask about the purpose of module "Computer_System". After clicking on the synthesis file, there are nearly 200 submodules in it, and some of them are garbled. I would like to ask whether those files are necessary for execution.

@@宋姿儀-o8w The module links the Verilog to the Qsys bus and is mostly generated by the compiler from the Qsys description. Qsys == Platform Designer

the benefit for the students is learning how to do it themselves.

code that is not written can do anything. sure, you could use the rising edge to get the timing, then analyse the sound perhaps with an FFT to detect specific frequencies.

@@ece4760 what does the FFT stands for?

@@SerBond007 google is your friend. en.wikipedia.org/wiki/Fast_Fourier_transform#:~:text=A%20Fast%20Fourier%20Transform%20(FFT,frequency%20domain%20and%20vice%20versa.

did you read the linked report?

terasic de1-soc with cyclone5

does SPARTAN 6 support this project? Like the vga and all..

@@durgaholla4338 I have no idea. Read the manual, then get ready to recode every detail.

First, you will note that this project is 9 years old, so any detailed memory is gone. The linked report mentioned a pot in the parts list, but no where else that I could find. Is that what you are refering to?

@@ece4760 Thank you for your reply! Yes that is the one I'm talking about. In the meantime i analyzed the linked report even further, and i assumed it is being used in the LCD circuit for the calibration of the contrast since there is no mention of it anywhere else, and there is no circuit for the LCD showed. Have a wonderful day!

@@adrianteiusanu The old LCDs did require a pot to set contrast. They did not include it, because it was a stanadard part of the class infrastructure at the time.

some sram (cyclone5 m10k) requies an explicit wait-state while reading.

@@ece4760 Thanks. I didn't know that either. I've been meaning to try adding SRAM to at least one of the FPGA boards I've bought, but I haven't made a start on it yet. I can buy ready made SDRAM boards for a DE10-Nano, but I wouldn't really know where to start with using that sort of memory.

@@TooSlowTube the sram we use is part of the fpga, not added on. SDRAM on the DE!-soc is handled by the QSYS platform designer tool.

@@ece4760 I see. I thought this was using the physical SRAM chip on the DE2 board. I've looked at an example using QSYS, for the DE10-Nano, but it seemed really awkward and cumbersome. I found the user interface for making connections pretty annoying - it seemed to be disconnecting lines as i was trying to add more connections, like a bad dream. I was thinking of digital audio applications where it's important to get consistent timing, which seems easier to do with SRAM, even though it doesn't need to be particularly quick. Since I'm mostly doing it to learn FPGA programming, it would be nice to stick to all Verilog, so I have code for all of it, ideally without any black boxes of IP that I don't get to look in.

@@TooSlowTube you do not need qsys for on-chip sram, and you canwrite all in Verilog, but Quartus will infer IP from your verilog to build memory using m10k blocks.

they used a small wall-wart 12 v supply

@@ece4760 Thank you!

anything you make yourself is hard, even if it already exists

did you read the linked report?

Did you read the linked report? What are you really asking?

this project is 4 years old, so I doubt that the students will respond. The only documentation is the linked report. Sorry.

4.5 Flex sensor Vibration motor

cornell university, masters project

did you read the linked report? It is not, you could always pport the program.

did you read the linked report?

Please be more specific with the question. what do you mean by ‘translated”.

​@@ece4760 how you created that map.. Thn how it is linked with code and fpga kit

@@Adeeshwarinaik the linked report has the only information on this project. acording to the report, a jpg of the rail system was converted to a bmp file, then converted to a C header file.

@@ece4760 actually I didn't understand that conversion part.. Can you suggest some reference for that pls

did you read the linked report?

I believe that the music was open source background music from one of scores of web sites.

for decades data went over analog phone line as tones. look up ‘acoustic modem’

I just opened it with no password. None required.

I consider student video to be the property of the student(s). They have to explicitly allow me to put it up. They can withdraw that permission at any time. I have taken a few down over the years.

thank you@@ece4760