#1 Why verilog is a popular HDL | properties of verilog Language

Verilog Language is a very famous and widely used programming language to design digital IC . In this tutorial, I will cover the properties of verilog language. After watching this video , you will get to know why verilog is famous HDL and widely used programming language among digital designer.
Lesson-1 Why verilog is a popular HDL • #1 Why verilog is a po...
Lesson-2 Operators in verilog(part-1) • #2 Operators in Veril...
Lesson-2 Operators in verilog(part-2) • Operators in Verilog (...
Lesson-2 Operators in verilog(part-3) • Operators in Verilog( ...
Lesson-3 Syntax in verilog • #3 Syntax in Verilog ...
Lesson-4 Data types in verilog • #4 Data types in veril...
Lesson-5 Vector and Array in verilog • #5 {Error:check descri...
Lesson-6 Modules and port in verilog • #6 Module and port de...
Lesson-7 Gate level modelling in verilog • #7 Gate level modelin...
Lesson-8 Dataflow Modeling in verilog • #8 Data flow modeling...
Lesson-9 Behavioral Modeling in verilog • #9 Behavioral modelli...
Lesson-10 Structural Modeling in verilog • #10 How to write veri...
Lesson-11 always block in verilog • #11 always block in V...
Lesson-12 always block for combinational logic • #12 always block for c...
Lesson-13 sequential logic in design • #13{Mistake:check desc...
Lesson-14 always block for sequential logic • #14 always block for s...
Lesson-15 Difference between latch and flip flop • #15 Difference betwee...
Lesson-16 Synchronous and Asynchronous RESET • #16(MISTAKE-Read Descr...
Lesson-17 Delays in verilog • #17 Delays in verilog ...
Lesson-18 Timing control in verilog • #18 Timing control in ...
Lesson-19 Blocking and Nonblocking assignment • #19 Blocking vs Non Bl...
Lesson-20 inter and intra assignment delay in verilog • #20 Inter and intra as...
Lesson-21 Why delays are not synthesizable • #21 Why delays are not...
Lesson-22 TESTBENCH writing in verilog • #22 How to write TESTB...
Lesson-23 Multiple always block in verilog • #23 Multiple ALWAYS bl...
Lesson-24 INITIAL block in verilog • #24 INITIAL block in v...
Lesson-25 Difference between INITIAL and ALWAYS block in verilog • #25 Difference between...
Lesson-26 if else in verilog • #26 if-else in verilog...
Lesson-27 CASE statement in verilog • #27 "case" statement i...
Lesson-28 CASEX and CASEZ in verilog • #28 casex vs casez in ...
Lesson-29 FOR loop in verilog • #29 "for" loop in veri...
Lesson-30 WHILE loop in verilog • #30 "while" loop in ve...
Lesson-31 FOREVER in verilog • #31 " forever " in ver...
Lesson-32 REPEAT in verilog • #32 " repeat " in veri...
Lesson-33 GENERATE in verilog • #33 "generate" in veri...
Lesson-34 FORK-JOIN in verilog • #34 " fork and join " ...
Lesson-35 named block in verilog • #35 Named block in ver...
Lesson-36 TASK in verilog • #36 (MISTAKE-Read Desc...
Lesson-37 FUNCTION in verilog • #37 (MISTAKE-Read Desc...
Lesson-38 WIRE vs REG in verilog • #38 Wire vs Reg | when...
Lesson-39 FSM-MEALY state machine in verilog • #39 Finite state machi...
Lesson-40 FSM- MOORE state machine in verilog • #40 Finite state machi...
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[@rushikeshkarande3207]

Hello, Very Very Good Contents are here. Thank you sir for making this. Can you please make videos on `timescale with more examples which one of the tricky part in Verilog.

[@ComponentByte]

Thank you for your appreciation. Timescale are for simulation purpose but for real hardware design(synthesis part) we don't much bother about it. I will make one video on it to explain how it is used and what exactly it represents. Thanks.

[@ranis1587]

Thank you sir This scours is very much knowledgeable So request to you please complit full course so learning is go on goooooo. Big thank sir

[@ComponentByte]

Most welcome. Wish you a happy learning. I will try to share my knowledge as much as possible. Thanks.

[@ranis1587]

@@ComponentByte sir please faste upload video so learning not stopped And enjoy learning very well

[@priyashalini6422]

Hi Sir could you please upload system verilog videos and uvm videos and perl scripting videos

[@nenadmilutinovic4752]

Hello, can you recommend some books to accompany this series of lectures?

[@ComponentByte]

There many great books available in PDF format on internet. If you explore then you will definitely get it's benefits. So I am not recommending you any specific Book. Please take help of internet.

[@sivarahuls3960]

can u explain the library fabrication synthesis part as i am new one to learn i had already spoke with U ihave 0 knowledge in electronic as I am a first year graduate so these videos are enouugh and i can learn through this right

[@ComponentByte]

Synthesis topic i have already covered in one of tutorial (frontend design tutorial and RTL tutorial )

[@sivarahuls3960]

@@ComponentByte thank you bro

[@durgesh1227]

Hey, I am a third year undergraduate student. I wish to learn about verilog. Shall I start with these video lectures or shall I revise the basics of Digital and Analog electronics first and then these videos?

[@ComponentByte]

Analog electronics is not required. Basics of digital electronics is must, only basic is enough .Then you can watch these videos and hopefully you will learn verilog coding

[@durgesh1227]

@@ComponentByte Thanks a lot. I will try to learn as much as I can.

[@rishabhsahu386]

Bro ..can you please provide pdfs of all lectures...it will be very helpful.

[@ComponentByte]

Hello, sorry to say you that Sharing the content prepared by me is not possible (even though I really wanted to share) due to the fear that the content may be available on internet by someone. Last time I shared one of my content with someone and unfortunately I found the same content on one file sharing site.since then I am not sharing with any one due to the fear of copyright. Hope you understand.

[@rishabhsahu386]

@@ComponentByte alright brother...no problem, i can understand.

[@lohithavenkyofficial2480]

Could you provide your number

[@rishabhsahu386]

@@ComponentByte bro, are your lectures are sufficient for learning Verilog or i should go with nptel lectures too along with yours?

[@ComponentByte]

It depends on you. If you feel you are not satisfied with my content then you can always look for alternative. I have created this KZbin channel because it's the only channel on KZbin where you can learn every concept of verilog and ask your query. Verilog concepts can't be learned from a College professor (NPTEL) as they have no industrial experience. But still I will motivate you to gain verilog knowledge as much as possible from whatever the source is.Thanks.

[@Akash-mh8tl]

Sir can i get this notes

[@sivarahuls3960]

what is a library bro

[@vishalmoladiya2735]

Thanks

[@serasen8316]

What is gate level netlist ?

[@ComponentByte]

It describes how various components (here baic gates) are connected. It's in text form. Netlist means list of nets . Nets mean connection . Gate level Netlist means how various gates are connected. It's just a description about this connection.Thanks

[@naiyarafzal6740]

If possible plz provide the ppt ,it will be helpful to us ❤️

[@ComponentByte]

I can't share these PPT because of copyright issue which i have already explained. Sorry. But I will be always there to help if any raises any kind of query regarding verilog or related to Thanks.

[@mukappakk3827]

What is the full form of RTL?

[@ComponentByte]

Register transfer level (RTL) is a technique to design digital logic in terms of register ( as storage ) and combinational logic. We use verilog HDL to achieve it. RTL provides the real Hardware for the logic we have written code. Hope it helps.

[@monisharavinda7982]

Register Transfer Level [RTL]

[@siddharthsahu6573]

Hitesh Dholakia