Introduction to Verilog HDL

[@an9291]

I didn't find any tutorials on these topics explained well. Definitely, this course will be helpful for many others like me. Thank you so much for this course.

[@ComponentByte]

Thank you. I didn't find any good tutorial on Verilog (on KZbin) and this is the reason I tried my best to make content on Verilog (not just theory but explanation of verilog code in terms of hardware) Hope it helps other.

[@yasht28-s8d]

God bless you! for providing such value to the students like me who can afford to buy online courses.

[@govindadharmaraju127]

its really a priceless playlist.

[@anahimeza5743]

Thanks for the explanation, I am gonna watch all the course it's really helpful. Greetings from Mexico

[@ComponentByte]

Welcome , if you are OK with my native accent then contents are for you.wish you a happy learning.Thanks.

[@anahimeza5743]

@@ComponentByte Thank you, I can understand very well:)

[@longnguyenhoang764]

So helpful, such a priceless course, many thanks!!!

[@venkateshiyer5073]

I have started today. I hope I can maintain consistency and learn in the best possible way !

[@ComponentByte]

Wish you a happy learning. Feel free to ask your query. I will try my best to answer .

[@venkateshiyer5073]

@@ComponentByte thank you sir!kindly check your mail sir !

[@GautamKumar-eo7jj]

I really enjoyed and learn and understood the syllabus of verilog. I am very excited to continue all the videos but sir all the contents are not in your channel. Please provide all the content and videos in best form. So that this channel will become best in verilog on KZbin.

[@MaheshBabu-ee3ti]

bro may I know your current status .. i mean did u get job in vlsi core?..i am yet to do mtech in vlsi

[@satyamsingh-xv7wg]

How much time it will take you for upload all this topic? This is the best way you doing. Please be specific after some time you will get better view so please stick to the verilog full course. Thanks

[@ComponentByte]

Thanks Satyam for your valuable comments. More than 40 lectures I will upload to cover all the basics of verilog. Then I will upload realtime concepts like digital filter design, low end protocols like SPI,I2C and then FPGA implementation . I will also cover how to write RTL code.so it will take time. This tutorial is for someone who wants to learn verilog form basics and who can't afford to join a VLSI TRAINING centre( I don't want this verilog language to be a commodity which someone can't afford ). I can upload random verilog content but it may confuse a beginner .so I upload the content , always thinking myself as a beginner in verilog. I am sharing my knowledge and experience. If it helps someone in anyway then I will be more than happy. I believe Sharing is the first step of humanity.

[@satyamsingh-xv7wg]

Thanks . Keep it up bro.

[@raghureddy265]

Super sir, explanation is very nice , 👌👌👌 thank you sir... Plzz upload complete course....

[@MaheshBabu-ee3ti]

bro may I know your current status .. i mean did u get job in vlsi core?..i am yet to do mtech in vlsi

[@saivineeth6032]

All videos are helpful and please provide system verilog videos also if possible

[@ComponentByte]

I have dropped my initial plan of uploading SV due to various reasons. Sorry. But VLSI related content will be uploaded continuously along with some useful knowledge.Thanks.

[@naseemsultana7942]

All videos are helpful Sir.If you could cover SV, UVM and any scripting language. Really appreciate your effort. Thank you once again.

[@ComponentByte]

Thank you. Due to some reason (I have already mentioned the reason) I won't be posting SV videos. Sorry. But I will keep posting vlsi related information.

[@kotteswariR]

sir, great job. can u plz upload the real time concept like I2C,SPI

[@ComponentByte]

Yes, I will definitely upload SPI, I2C protocols.

[@MaheshBabu-ee3ti]

bro may I know your current status .. i mean did u get job in vlsi core?..i am yet to do mtech in vlsi

[@harihemanth04]

Thank you😮😊

[@santosh_bhavar1303]

Thise course will help vlsi engineer , which is a beginner??

[@ComponentByte]

I am trying to share the knowledge I have gained over the years so that freshers don't spend their quality time over something which they should not. A service from my side to all those who needs a little awareness.

[@santosh_bhavar1303]

@@ComponentByte i am starting this course today , i hope at the end , i learn so much 😊💯✨

[@ComponentByte]

I will be always there if query arises.

[@hossamsamir1141]

Which program environment will we use ? and how can i install it ?

[@ComponentByte]

XILINX ISE and Modelsim are free tools, students version available for free in XILINX and modelsim website. It's very easy to install and work with. It's enough for practising.Thanks.

[@priyashalini6422]

Digital logic design course also explain sir

[@ComponentByte]

Yes, i will do it for sure.

[@sanyamjain8225]

Is this Verilog Playlist enough from interview point of view for a Btech Fresher?

[@ComponentByte]

This verilog playlist is enough for verilog related questions asked during interview but not for whole interview. Please watch RTL/VLSI interview questions I have uploaded and you will get idea about which type of questions are asked.

[@learnwithrr1230]

Hello sir kindly complete the course as it is not complete.

[@ComponentByte]

These days I am not getting time to upload vlsi related stuff. It will take time but I will also try to upload content other than VLSI. Thanks.

[@09lavakrishna42]

hello sir you didn't covered RAM,ROM,FIFO,PROTOCALS,INTERFACING,PERL sir , When you will upload

[@ComponentByte]

Due to workload I am unable to upload content. I had uploaded all the contents during lockdown. But as I have promised I will definitely do it. I will upload each concept I had mentioned.

[@vishal_moladiya_music]

Thanks

[@ComponentByte]

Welcome.

[@BHARATGUPTA-xg8lj]

sir , is there any telegram you have . please mention ???

[@ComponentByte]

No telegram. I have no idea about it except it's a name of newspaper.

[@yobyag]

Sir pls start system verylog and scripting

[@sachinkulal8345]

👌👍💥

[@raunakgiri21]

Hi, ASTU students