14.17. Glitches and logical hazards

[@adbanerjee9888]

I have an intuitive understanding of why CLBs with inertial delays might block glitches with widths smaller than the inertial-delay width. The way I look at it is, if the inertial-delay time width is narrower than the glitch width, the sampling time will not even register the glitch as valid data. Is this a correct understanding? Also, is there a more quantitative explanation or resource to understand this further?