4.5 - Timing Hazards & Glitches

You learn best from this video if you have my textbook in front of you and are following along. Get the book here: amzn.to/32IbAaN. This video covers a portion (see title of video!) of the textbook "Introduction to Logic Circuits & Logic Design with VHDL" by Brock LaMeres. I also have a Verilog version of this textbook, which you can get here: amzn.to/2FDCs2Q.

[@westcountrybob2521]

I am aged 72 and read and watch this type of information just as an exercise for my mind. To date this is the clearest explanation of how this electronic problem occurs and how a solution is derived.

[@mashai1161]

Great respect!

[@oreoluwaolukotun7040]

Thank you so much. Funny how my college professor that I pay thousands of dollars to learn from could never explain like this.

[@christopherrobin5693]

@Yoshi Licks some people aren't cut out for teaching and the OP has a point. This content is forced down Comp Sci majors throats and these more advanced digital logic concepts are beyond pale of what many of use will encounter in our career paths. It's a bonafide $#!Tshow when non-EENG majors have to put up with w professors that have terrible teaching skills.

[@christopherrobin5693]

Agreed. Professors who assume comp sci majors take this class because we want to are morons when they assume we have the pre-requisites and passion electrical engineering majors will have approaching this class. When they can't teach, it just makes it that much more of a $#!T show....

[@moyeonkim]

Thank you for the easy explanation but I thought my ears were gonna blow out from the exhales XD

[@stargazeronesixseven]

Glitches in Time~Space causing Hazards to Missing People >>> Thank You So Much for the electronic Time Glitches Hazard tutorial , hopefully might explained & point us towards the Correct Logic of what happened to these Missing People?! ...

[@zinchen7209]

amazing concept to realize the glitch and solution, thanks sir !

[@chuhangm3791]

Those steps are super clear! Thank you sir ;)

[@bethanylopez4585]

This helped me understand glitches and propagation delays after learning it in class.

[@genricksoncarcedo7013]

Very clear explanation! Thanks!

[@atipatbeau1174]

now i understand thank you!

[@azultarmizi]

This is very clear!

[@aaa2220]

thanks completely understand the concept!

[@NickVrahoretis]

Awesome! This is really helpful

[@farukben]

Your mic is great sir :D

[@heyuehon4206]

nice one. Sir I hope you can upload more video about digital system. It is very useful for me :) THX A LOT!!!!!!

[@amradel7920]

Beauty. Absolute beauty.

[@Sevdiklerimiz2]

Thank You !!

[@exedrak]

Thank you

[@yogeshlyrics6567]

Dhoooooooor bhawa

[@derjemand1021]

Thank you sir

[@ahmedkhalil9917]

very helpful thanks sir

[@unchaynd7266]

Do static-1 timing hazards only occur when the circuit is transitioning from one prime implicant to another?

[@digitallogicprogramming2199]

Yes

[@arunkrishna2669]

What about clocking the combinational ckt... And provide clock skewing

[@stutisharon5920]

Hi Sir, Why isnt there 1ns of propagation delay initially at B.C, since for the 1AND1 to propagate through the AND gate, and appear at its output, it would take 1ns. Why are we assuming that B.C would also turn 1 at time= 0. Kindly clarify, if I am understanding this wrong. Regards, Sharon

[@tugceyldz426]

How could I draw circuit model using timing diagram?

[@matambasavaraju3430]

Whoa what a question

[@farukben]

Write down the truth table and create your circuit using it

[@domulko44]

thanks a lot :)

[@mostafaalsa4605]

Shouldn't be there a 1 ns delay in 8:54 before turning from 0 in to 1?

[@angeladelosreyes701]

This is also what im thinking

[@Karim-tt1sj]

Im confused right at the moment when i thought i got it gasped he did this!

[@leonpeplau4710]

@@Karim-tt1sj same

[@Karim-tt1sj]

@@leonpeplau4710 i understood it rn, the plot is that the glitch takes a while (1ns) to happen but the duration of the glitch will not be extended by 1ns ... It will be 1ns .

[@ramenruler4601]

good explanation but mic quality is a little annoying

[@bestyav5529]

Nice .I give you a big hand

[@dj_gzero]

Wait I’m confused as to why it took c’ a nano second delay to go from 0 to 1 but there was no delay for c to go from 1 to 0

[@apfeline4695]

because c´is the inverted c, which means it has to go thorugh the inverter which causes the delay

[@yogeshlyrics6567]

Tuch marda chiknya mst re

[@asieraristizabal9985]

dude giving a lecture at 3fps

[@potatobits7997]

annoying mic

[@lucyfabulous]

耳机党阵亡😊